Packaging test chip for flip-chip and wire bonding process characterization

2004 ◽  
Author(s):  
J. Schwizer ◽  
Wan Ho Song ◽  
M. Mayer ◽  
O. Brand ◽  
H. Baltes
Keyword(s):  
Flip Chip ◽  
Wire Bonding ◽  
Bonding Process ◽  
Test Chip ◽  
Process Characterization

Failure Analysis on Power Trench MOSFET Devices with Copper Wire Bonds

2011 ◽  
Author(s):  
Huixian Wu ◽  
Arthur Chiang ◽  
David Le ◽  
Win Pratchayakun
Keyword(s):  
Failure Analysis ◽  
Copper Wire ◽  
New Technology ◽  
Analytical Techniques ◽  
Wire Bonding ◽  
Bonding Process ◽  
Wire Bonds ◽  
Copper Wire Bonding ◽  
Wet Chemical ◽  
Microelectronic Components

Abstract With gold prices steadily going up in recent years, copper wire has gained popularity as a means to reduce cost of manufacturing microelectronic components. Performance tradeoff aside, there is an urgent need to thoroughly study the new technology to allay any fear of reliability compromise. Evaluation and optimization of copper wire bonding process is critical. In this paper, novel failure analysis and analytical techniques are applied to the evaluation of copper wire bonding process. Several FA/analytical techniques and FA procedures will be discussed in detail, including novel laser/chemical/plasma decapsulation, FIB, wet chemical etching, reactive ion etching (RIE), cross-section, CSAM, SEM, EDS, and a combination of these techniques. Two case studies will be given to demonstrate the use of these techniques in copper wire bonded devices.

scholarly journals Design and Switching Characteristics of Flip-Chip GaN Half-Bridge Modules Integrated with Drivers

2021 ◽  
Vol 11 (15) ◽  
pp. 7057
Author(s):  
Lin Wang ◽  
Zhe Cheng ◽  
Zhi-Guo Yu ◽  
De-Feng Lin ◽  
Zhe Liu ◽  
...  
Keyword(s):  
Flip Chip ◽  
High Electron Mobility Transistors ◽  
Wire Bonding ◽  
High Electron ◽  
Parasitic Inductance ◽  
Switching Performance ◽  
Turn On ◽  
Electron Mobility Transistors ◽  
Chip Technology ◽  
Switching Characteristics

Half-bridge modules with integrated GaN high electron mobility transistors (HEMTs) and driver dies were designed and fabricated in this research. Our design uses flip-chip technology for fabrication, instead of more generally applied wire bonding, to reduce parasitic inductance in both the driver-gate and drain-source loops. Modules were prepared using both methods and the double-pulse test was applied to evaluate and compare their switching characteristics. The gate voltage (Vgs) waveform of the flip-chip module showed no overshoot during the turn-on period, and a small oscillation during the turn-off period. The probabilities of gate damage and false turn-on were greatly reduced. The inductance in the drain-source loop of the module was measured to be 3.4 nH. The rise and fall times of the drain voltage (Vds) were 12.9 and 5.8 ns, respectively, with an overshoot of only 4.8 V during the turn-off period under Vdc = 100 V. These results indicate that the use of flip-chip technology along with the integration of GaN HEMTs with driver dies can effectively reduce the parasitic inductance and improve the switching performance of GaN half-bridge modules compared to wire bonding.

scholarly journals Optimal Parameter Design for IC Wire Bonding Process by Using Fuzzy Logic and Taguchi Method

IEEE Access ◽  
2016 ◽  
Vol 4 ◽  
pp. 3034-3045 ◽  
Author(s):  
Jinn-Tsong Tsai ◽  
Cheng-Chung Chang ◽  
Wen-Ping Chen ◽  
Jyh-Horng Chou
Keyword(s):  
Fuzzy Logic ◽  
Taguchi Method ◽  
Optimal Parameter ◽  
Wire Bonding ◽  
Bonding Process ◽  
Parameter Design
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