Cost analysis: solder bumped flip chip versus wire bonding

2000 ◽  
Vol 23 (1) ◽  
pp. 4-11 ◽  
Author(s):  
J.H. Lau
Keyword(s):  
Cost Analysis ◽  
Flip Chip ◽  
Wire Bonding

scholarly journals Design and Switching Characteristics of Flip-Chip GaN Half-Bridge Modules Integrated with Drivers

2021 ◽  
Vol 11 (15) ◽  
pp. 7057
Author(s):  
Lin Wang ◽  
Zhe Cheng ◽  
Zhi-Guo Yu ◽  
De-Feng Lin ◽  
Zhe Liu ◽  
...  
Keyword(s):  
Flip Chip ◽  
High Electron Mobility Transistors ◽  
Wire Bonding ◽  
High Electron ◽  
Parasitic Inductance ◽  
Switching Performance ◽  
Turn On ◽  
Electron Mobility Transistors ◽  
Chip Technology ◽  
Switching Characteristics

Half-bridge modules with integrated GaN high electron mobility transistors (HEMTs) and driver dies were designed and fabricated in this research. Our design uses flip-chip technology for fabrication, instead of more generally applied wire bonding, to reduce parasitic inductance in both the driver-gate and drain-source loops. Modules were prepared using both methods and the double-pulse test was applied to evaluate and compare their switching characteristics. The gate voltage (Vgs) waveform of the flip-chip module showed no overshoot during the turn-on period, and a small oscillation during the turn-off period. The probabilities of gate damage and false turn-on were greatly reduced. The inductance in the drain-source loop of the module was measured to be 3.4 nH. The rise and fall times of the drain voltage (Vds) were 12.9 and 5.8 ns, respectively, with an overshoot of only 4.8 V during the turn-off period under Vdc = 100 V. These results indicate that the use of flip-chip technology along with the integration of GaN HEMTs with driver dies can effectively reduce the parasitic inductance and improve the switching performance of GaN half-bridge modules compared to wire bonding.

Development of Lead-Free Flip Chip Package and Its Reliability

2003 ◽  
Author(s):  
Jeffrey C. B. Lee ◽  
Sting Wu ◽  
H. L. Chou ◽  
Yi-Shao Lai
Keyword(s):  
Failure Mode ◽  
Flip Chip ◽  
Failure Modes ◽  
Solder Bump ◽  
Wire Bonding ◽  
Point Of View ◽  
Lead Free ◽  
Temperature Cycle ◽  
Snagcu Solder ◽  
Temperature Cycle Test

SnAgCu solder used in laminate package like PBGA and CSP BGA to replace eutectic SnPb as interconnection has become major trend in the electronic industry. But unlike well-known failure mode of wire bonding package, flip chip package with SnAgCu inner solder bump and external solder ball as electrical interconnection present a extremely different failure mode with wire-bonding package from a point of view in material and process. In this study, one 16mm×16mm 3000 I/O SnAgCu wafer bumping using screen-printing process was explored including the effects of reflow times, high temperature storage life (HTSL) and temperature cycle test (TCT) on bump shear strength. Furthermore, the qualified wafer bumping is assembled by flip chip assembly with various underfill material and specific organic build-up substrate, then is subject to MSL4/260°C precondition and temperature cycle test to observe the underfill effect on SnAgCu bump protection and solder joint life. Various failure modes in the flip chip package like solder bump, underfill and UBM and so on, will be scrutinized with SEM. And finally, best material combination will be addressed to make the lead free flip package successful.

Mechanism and Model of Bond Formation in Ultrasonic Wire Bonding

2015 ◽  
Author(s):  
T. Calvin Tszeng
Keyword(s):  
Flip Chip ◽  
Critical Phenomenon ◽  
Bond Formation ◽  
Interfacial Shear Stress ◽  
Wire Bonding ◽  
Micromechanics Model ◽  
Ultrasonic Bonding ◽  
Microelectronic Devices ◽  
Ultrasonic Wire Bonding ◽  
Technological Significance

Despite being a critical phenomenon of tremendous technological significance in ultrasonic flip-chip and wire bonding processes of today’s microelectronic devices, interfacial bond formation still calls for better understanding at a fundamental level. The goal of the research is to improve these processes through better understanding and modeling of bond formation. This paper presents a micromechanics model that addresses increasing contact area during ultrasonic cyclic loading cycle. The micromechanics model provides interfacial shear stress as boundary condition to FEM simulations of ultrasonic bonding processes. Comparison between preliminary results and experimental data is conducted.

A cost effective PoP structure with high I/O density

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 000768-000785
Author(s):  
Hongjie Wang ◽  
Weidong Huang ◽  
Fei Geng ◽  
Yuan Lu ◽  
Bo Zhang ◽  
...  
Keyword(s):  
Solder Ball ◽  
Flip Chip ◽  
Solder Bump ◽  
Cost Effective ◽  
Wire Bonding ◽  
Manufacturing Cost ◽  
Good Reliability ◽  
Solder Bumps ◽  
Package Size ◽  
Interconnection Structure

Package-on-package (PoP) structure is widely used in smart phones and tablets in which memory package is directly attached to the top of the application processor. As the market demands more speed and bandwidth, memory devices need more than 1000 I/Os to support future requirements. However← since the package size also becomes smaller and smaller, finer I/O pitch is absolutely required. Although using some new technology can achieve finer I/O pitch, it increases the manufacturing cost. Using traditional mature technology can reduce manufacturing cost, but has limitation in finer I/O pitch. So, it demands a reasonable balance between design, process and cost to develop an applicable PoP structure. In this paper we proposed a novel and cost effective PoP interconnection structure and a multi-layer PoP model. The PoP interconnection was formed by the solder ball on the top package connected to the solder bumps on the bottom package. The solder bump was made of a smaller solder ball attached on a Cu stud bump on the top of bottom substrate. The Cu stud bump was made through wire bonding machines and was coined so that the small solder ball can be attached to it. Using film assist molding technology, a half of the solder ball is exposed outside of molding compound, which can be connected with the solder ball of the top package through reflow process. This PoP interconnection structure was named solder bump through molding (BTM). A three layer PoP vehicle package was designed in our experiments. The top package was a wire bonding BGA, the middle and bottom packages were both flip chip BGA with BTM interconnection structure. The package size of these three packages was 10×10mm2 and ball pitch was 0.4mm. The assembly process of top package was as normal as other wire bonding BGA. The assembly processes of middle and bottom packages were as follows: The Cu stud bumps were first bonded to the top surface of the substrate using wire bonding machines. Small solder balls were attached to the top of Cu stud bumps using stencil tool and then reflowed. After solder bumps were made, all chips were flip bonded to the substrates. Then, using film assist molding and MUF technology, the chips were encapsulated and Cu stud bumps were half exposed. After all the packages were ready, the package stacking and reflow was performed one by one from top to the bottom and the overall three layer PoP was formed. C-scan test and cross section analysis showed that the encapsulation had no voids in most samples. Electrical test results showed the interconnection was good. Reliability study will be also discussed in this paper, which is still in research now. In BTM structure, both Cu stud and solder ball attach can be easily realized. The ball pitch can be 0.4mm or smaller and the process is also applicable for more layer PoP. Thus, BTM PoP structure provides a good solution considering the balance among cost, performance and manufacturing for 3D package. Acknowledgments The authors acknowledge the support of National Science and Technology Major Project (Project number：2013ZX02501003).

Flip-Chip Technologies, Applications, Market Status and Forecasts

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 001797-001828 ◽  
Author(s):  
Christophe Zinck ◽  
Jean-Marc Yannou ◽  
Jérôme Baron ◽  
Phil Garou
Keyword(s):  
Power Distribution ◽  
Flip Chip ◽  
Lower Cost ◽  
Signal Propagation ◽  
Cmos Technology ◽  
Wire Bonding ◽  
Power Devices ◽  
Market Status ◽  
Bonding Technology ◽  
To Come

Renewed interest in flip-chip technologies in concurrently motivated in many application areas by such factors as the rising cost of gold used for wire bonding, the need for low thickness devices, continued CMOS downscaling, higher currents and temperatures, and lower voltages. Today, many sophisticated devices can no longer be packaged with wire bonding technology and the mobile applications are more and more requiring footprint and weight reduction coupled with higher electrical performances (signal propagation and power distribution). The emergence of the 28nm CMOS technology node in particular, poses new quality and reliability constraints on interconnect technologies so as to cope with the increasing fragility of the back end of line, which may disqualify wire bonding for good. Not to mention the ever increasing IO density, making it necessary to develop new bumping and substrate technologies. It is not any longer only about higher performance and lower cost reliable interconnect, assembly and packaging technologies: if remained unresolved, the above constraints will prove to be bottlenecks if not obstacles to the continuation of Moore's law. In this presentation, we will first focus on Flip-Chip technologies and their evolution. We will present the main players, their facilities and technologies. We will sketch a worldwide roadmap of flip-chip featuring such varied applications as wireless digital, PC processors, RF and power devices. We will then present our market forecasts and explain how we see these innovations will modify the market of packaging interconnections and assembly in the years to come.

Cost Analysis of Flip Chip Assembly Processes: Mass Reflow with Capillary Underfill and Thermocompression Bonding with Nonconductive Paste

2015 ◽  
Vol 2015 (1) ◽  
pp. 000702-000706
Author(s):  
Amy Palesko
Keyword(s):  
Cost Analysis ◽  
Flip Chip ◽  
Bonding Process ◽  
Cost Modeling ◽  
Future Cost ◽  
Process Flow ◽  
Package Size ◽  
Thermocompression Bonding ◽  
Capillary Underfill ◽  
Selection Of

Many factors affect the selection of the assembly and interconnect processes used to package a die. For example, the size of the die and package, the type of substrate, and the number of IOs all must be considered. In this paper, two processes are compared: a flip chip process using mass reflow with capillary underfill versus a flip chip thermocompression bonding process using nonconductive paste. Activity based cost modeling is used for the analysis. Both of the process flows are presented in detail, then multiple cost comparisons are presented. Examples of the variables that will change are package size, material cost, and equipment cost. In most cases, the bonding and material portions of the process flows are focused on rather than the entire assembly and substrate processes—this allows for a better analysis of particular details. Conclusions are drawn about which design scenarios are suitable for each process flow. Key cost drivers that may affect future cost comparisons as the technologies advance are also indicated.

Advances in Wire Bonding Technology for Different Bonding Wire Material

2015 ◽  
Vol 2015 (1) ◽  
pp. 000406-000412 ◽  
Author(s):  
Ivy Qin ◽  
Aashish Shah ◽  
Hui Xu ◽  
Bob Chylak ◽  
Nelson Wong
Keyword(s):  
Flip Chip ◽  
Technology Development ◽  
Copper Wire ◽  
Low Cost ◽  
Wire Bonding ◽  
Bonding Wire ◽  
Wire Material ◽  
Ball Bonding ◽  
Bonding Technology ◽  
The Right

With all the advances in 2.5D and 3D packaging, wire bonding is still the most popular interconnect technology and the workhorse of the industry. Wire bonding technology has been the lower cost solution comparing to flip chip. Wire bonding package cost is much reduced with the introduction of Copper wire bonding. Technology development and innovation in wire bonding provides new packaging solutions that improves performance and reduces cost. This paper reviews the recent innovations in ball bonding technology to provide optimized ball bonding solutions targeted for different bonding wire material. It examines the different challenges for the alternative wire types including Cu wire, Pd coated, and AuPd coated Cu wire and Ag Alloy wire. We will discuss key development in ball bonding equipment, process and material to overcome the challenges and provide robust low cost solutions. The advantages of each wire type are outlined, and guidelines to select the right bonding wire type per application requirements are provided.

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