Void formation failure mechanisms in integrated circuits

1969 ◽  
Vol 57 (9) ◽  
pp. 1594-1598 ◽  
Author(s):  
B. Selikson
Keyword(s):  
Integrated Circuits ◽  
Failure Mechanisms ◽  
Void Formation

Combine Micro-Probing and OBIRCH to Catch Non-Recognizable Fault in RF and Mixed-Mode Integrated Circuits

2007 ◽  
Author(s):  
Cha-Ming Shen ◽  
Yen-Long Chang ◽  
Lian-Fon Wen ◽  
Tan-Chen Chuang ◽  
Shi-Chen Lin ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Radio Frequency ◽  
Failure Analysis ◽  
Case Studies ◽  
Mixed Mode ◽  
Failure Mechanisms ◽  
Deep Submicron ◽  
Digital Logic ◽  
Successful Approach ◽  
Cmos Processes

Abstract Highly-integrated radio frequency and mixed-mode devices that are manufactured in deep-submicron or more advanced CMOS processes are becoming more complex to analyze. The increased complexity presents us with many eccentric failure mechanisms that are uniquely different from traditional failure mechanisms found during failure analysis on digital logic applications. This paper presents a novel methodology to overcome the difficulties and discusses two case studies which demonstrate the application of the methodology. Through the case studies, the methodology was proven to be a successful approach. It is also proved how this methodology would work for such non-recognizable failures.

Three-Dimensional Paddle Shift Modeling for IC Packaging

2004 ◽  
Vol 127 (3) ◽  
pp. 324-334 ◽  
Author(s):  
Chien-Chang Pei ◽  
Sheng-Jye Hwang
Keyword(s):  
Structural Analysis ◽  
Integrated Circuits ◽  
Three Dimensional ◽  
Void Formation ◽  
Model Performance ◽  
Computational Time ◽  
Pressure Loading ◽  
Filling Process ◽  
Molding Process ◽  
Incomplete Filling

The plastic packaging process for integrated circuits is subject to several fabrication defects. For packages containing leadframes, three major defects may occur in the molding process alone, namely, incomplete filling and void formation, wire sweep, and paddle shift. Paddle shift is the deflection of the leadframe pad and die. Excessive paddle shift reduces the encapsulation protection for the components and may result in failures due to excessive wire sweep. Computer-aided analysis is one of the tools that could be used to simulate and predict the occurrence of such molding-process-induced defects, even prior to the commencement of mass production of a component. This paper presents a methodology for computational modeling and prediction of paddle shift during the molding process. The methodology is based on modeling the flow of the polymer melt around the leadframe and paddle during the filling process, and extracting the pressure loading induced by the flow on the paddle. The pressure loading at different times during the filling process is then supplied to a three-dimensional, static, structural analysis module to determine the corresponding paddle deflections at those times. The paper outlines the procedures used to define the relevant geometries and to generate the meshes in the “fluid” and “structural” subdomains, and to ensure the compatibility of these meshes for the transfer of pressure loadings. Results are shown for a full paddle shift simulation. The effect on the overall model performance of different element types for the mold-filling analysis and the structural analysis is also investigated and discussed. In order to obtain more accurate results and in a shorter computational time for the combined (fluid and structural) paddle shift analysis, it was found that higher-order elements, such as hexahedra or prisms, are more suitable than tetrahedra.

A High Voltage Scanning Electron Microscope for the In-SituObservation and Recording of Electromigration Voids in Metal Lines on Integrated Circuits.

1997 ◽  
Vol 3 (S2) ◽  
pp. 615-616
Author(s):  
P. A. Flinn ◽  
S. Lee ◽  
J. C. Doan ◽  
J. C. Bravman ◽  
T. Marieb ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Void Formation ◽  
Time To Failure ◽  
Protective Film ◽  
Resolution Limit ◽  
Incubation Periods ◽  
Sample Test ◽  
Test Current ◽  
Voltage Scanning ◽  
Scanning Electron

The passing of current through thin metal lines results in the formation of voids which will eventually cause the line to fail electrically. Gathering of experimental data on electromigration has been limited by two facts: The dimensions of the metal lines on modern integrated circuits are on the order of the resolution limit of light microscopy; and voids in these lines behave quite differently when they are surrounded by a protective film of SiO2 or other dielectric. This dielectric protects the metal surface and constrains the line, pushing back on the metal displaced by void formation. Several additional factors further complicate experimental analysis: the sample test current must be precisely controlled during observation; the sample must be accurately heated to several hundred degrees; the metal lines must be long and narrow (typically 0.2-3.0 (am wide by 300 μm long); testing is often lengthy, sometimes extending over several days even under conditions selected to minimize the time to failure; and electromigration failures are characterized by long incubation periods during which no changes are observed followed by rapid and complex behavior.

Analysis for Evaluation of Threshold Current Density of Electromigration Damage in Taper-Shaped Metal Line

2017 ◽  
Author(s):  
Hiroki Kikuchi ◽  
Kazuhiko Sasagawa ◽  
Kazuhiro Fujisaki
Keyword(s):  
Integrated Circuits ◽  
Current Density ◽  
Evaluation Method ◽  
High Current Density ◽  
Void Formation ◽  
Threshold Current ◽  
Threshold Current Density ◽  
Cathode Side ◽  
Metal Line ◽  
Governing Parameter

Metal lines used in integrated circuits (ICs) become narrow for raising the device performance. Due to scaling down of the ICs, current density and Joule heating are increased, which induces electromigration (EM) damage. EM is transportation phenomena of metallic atoms caused by electron wind under high current density. EM leads to hillock and void formation in the metal line, thus EM should be considered to evaluate the performances of the device safe. It is known that a value of threshold current density which is critical current density of the EM damage exists in via-connected and passivated lines. In this study, the effect of line geometry on the threshold current density is discussed in the case of taper-shaped line. The evaluation method of threshold current density is conducted based on numerical simulation technique with building-up processes of atomic density distribution in the metal line by using a governing parameter of EM damage. As the simulation results, threshold current density increased in the cases of shorter line length, lower temperature, and wider width in cathode side. Furthermore, a new parameter was proposed for simplified evaluation of the threshold current density in taper-shaped lines. The evaluation method is able to apply various line shapes and conditions and it is expected to use for confirmation of the reliability of the lines in circuit design processes.

Electromigration Failure of Narrow Al Alloy Conductors Containing Stress - Voids

1994 ◽  
Vol 338 ◽  
Author(s):  
A. S. Oates ◽  
J. R. Lloyd
Keyword(s):  
Integrated Circuits ◽  
Temperature Dependence ◽  
Failure Mechanisms ◽  
Al Alloy ◽  
Stress Gradients ◽  
Failure Times ◽  
Effects Of Stress ◽  
The Impact

ABSTRACTElectromigration and stress - induced voiding are two of the most important metallization failure mechanisms for integrated circuits. These mechanisms are not independent since stress voiding may affect electromigration. In this paper we examine the impact of stress voiding on electromigration failure of narrow Al alloy stripes, and show that the major effects of stress voiding are significant reductions in failure times, and a non-Arrenhius temperature dependence of the lifetime. We propose a model to explain these effects based on the formation of flux divergences at pre-existing voids due to stress gradients.

Structural and compositional effects on the electron migration properties of Al-Cu alloy

1992 ◽  
Vol 50 (2) ◽  
pp. 1420-1421
Author(s):  
J.B. Liu ◽  
J.Z. Duan ◽  
R. Gronsky
Keyword(s):  
Integrated Circuits ◽  
Void Formation ◽  
Substrate Bias ◽  
Factors Affecting ◽  
Cu Alloy ◽  
Electron Migration ◽  
Service Application ◽  
The Individual ◽  
Silicon Based

Aluminium and aluminium-based alloys are typically used as the metallization interconnections in LSI and VLSI silicon-based integrated circuits. Important factors affecting the lifetime and reliability of these interconnections in IC devices are the individual microstructures, device layer combinations, electron migration, and stress migration that occur during their fabrication and their in-service application. There are many possible remedies for each of these factors. The use of bias sputtering or “planarization” has been shown to improve the quality of the interconnection greatly. Recently, some studies have revealed a new planarization technique involving sputter deposition of Al alloys at elevated temperature without any substrate bias, combined with a TiN precoating to reduce the migration of Al atoms. In this paper, the microstructure of Al-0.2Cu/TiN/SiO2/Si under optimum lifetime conditions is assessed, and a mechanism of void formation is proposed to explain the observations.A representative TEM cross section image of Al-0.2% Cu sputtered at 100 V bias and at substrate temperature 450°C with a TiN/SiO2 prercoating is shown in Fig.l. The surface topography of the Al-Cu alloy is shown for comparison purposes in Fig.2.

Reliability Assessment: New Tools for the Next Generation of Packages

2008 ◽  
Vol 5 (2) ◽  
pp. 44-51
Author(s):  
Isabelle Bord ◽  
Bruno Levrier ◽  
Yannick Deshayes ◽  
Laurent Béchou ◽  
Yves Ousten
Keyword(s):  
Integrated Circuits ◽  
Acoustic Analysis ◽  
Failure Mechanisms ◽  
Reliability Assessment ◽  
Integrated Systems ◽  
Principal Support ◽  
Next Generation ◽  
X Ray ◽  
Plastic Packages

Reliability assessment of components, integrated circuits, and microassemblies is clearly identified as a major factor in the on-going development of microelectronics. Since the last decade, the 3-D packaging and interconnections have emerged, and integrated packages have been developed. System-in-package (SIP) has become the principal support for integrated systems. Numerous problems are linked to their decreasing dimensions, the increasing numbers of interfaces (multichips stacked one on top of another), and plastic packages that must tolerate higher temperatures (RoHS). How is the reliability of such components assessed? What are the tools to investigate failure mechanisms in these new packages? This article gives some solutions mixing acoustic analysis, x-ray microscopy, electrical testing, and the use of specific tests points (sensors) placed in the package.

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