Path Delay Fault Test Set for Two-Rail Logic Circuits

2008 ◽  
Author(s):  
Kazuteru Namba ◽  
Hideo Ito
Keyword(s):  
Logic Circuits ◽  
Path Delay ◽  
Test Set ◽  
Delay Fault ◽  
Path Delay Fault

scholarly journals A Novel Path Delay Fault Simulator Using Binary Logic

VLSI Design ◽  
1996 ◽  
Vol 4 (3) ◽  
pp. 167-179 ◽  
Author(s):  
Ananta K. Majhi ◽  
James Jacob ◽  
Lalit M. Patnaik
Keyword(s):  
Logic Circuits ◽  
Experimental Results ◽  
Path Delay ◽  
Delay Fault ◽  
Rule Based ◽  
Binary Logic ◽  
Multiple Valued Logic ◽  
Path Delay Fault ◽  
Combinational Logic Circuits ◽  
Rule Based Approach

A novel path delay fault simulator for combinational logic circuits which is capable of detecting both robust and nonrobust paths is presented. Particular emphasis has been given for the use of binary logic rather than the multiple-valued logic as used in the existing simulators which contributes to the reduction of the overall complexity of the algorithm. A rule based approach has been developed which identifies all robust and nonrobust paths tested by a two-pattern test <V1,V2>, while backtracing from the POs to PIs in a depth-first manner. Rules are also given to find probable glitches and to determine how they propagate through the circuit, which enables the identification of nonrobust paths. Experimental results on several ISCAS'85 benchmark circuits demonstrate the efficiency of the algorithm.

A new classification of path-delay fault testability in terms of stuck-at faults

2004 ◽  
Vol 19 (6) ◽  
pp. 955-964 ◽  
Author(s):  
Subhashis Majumder ◽  
Bhargab B. Bhattacharya ◽  
Vishwani D. Agrawal ◽  
Michael L. Bushnell
Keyword(s):  
Path Delay ◽  
New Classification ◽  
Delay Fault ◽  
Path Delay Fault
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