On the design of path delay fault testable combinational circuits

[1990] Digest of Papers. Fault-Tolerant Computing: 20th International Symposium ◽

10.1109/ftcs.1990.89391 ◽

2002 ◽

Cited By ~ 78

Author(s):

A.K. Pramanick ◽

S.M. Reddy

Keyword(s):

Path Delay ◽

Combinational Circuits ◽

Delay Fault ◽

Path Delay Fault

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New advances in path delay fault testing of combinational circuits

Proceedings of IEEE VLSI Test Symposium ◽

10.1109/vtest.1994.292301 ◽

2002 ◽

Cited By ~ 3

Author(s):

X. Xie ◽

A. Albicki

Keyword(s):

Path Delay ◽

Combinational Circuits ◽

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

Path Delay Fault ◽

Path Delay Fault Testing

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An Enhanced Path Delay Fault Simulator for Combinational Circuits

2011 14th Euromicro Conference on Digital System Design ◽

10.1109/dsd.2011.52 ◽

2011 ◽

Cited By ~ 1

Author(s):

P. Manikandan ◽

Bjorn B. Larsen ◽

Einar J. Aas

Keyword(s):

Path Delay ◽

Combinational Circuits ◽

Delay Fault ◽

Path Delay Fault

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Design of robust-path-delay-fault-testable combinational circuits by Boolean space expansion

Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors ◽

10.1109/iccd.1992.276321 ◽

2003 ◽

Cited By ~ 3

Author(s):

X. Xie ◽

A. Albicki ◽

A. Krasniewski

Keyword(s):

Path Delay ◽

Combinational Circuits ◽

Delay Fault ◽

Boolean Space ◽

Path Delay Fault ◽

Space Expansion

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On full path delay fault testability of combinational circuits

Proceedings of IEEE 3rd Asian Test Symposium (ATS) ◽

10.1109/ats.1994.367213 ◽

2002 ◽

Author(s):

Xiaodong Xie ◽

A. Albicki

Keyword(s):

Path Delay ◽

Combinational Circuits ◽

Delay Fault ◽

Path Delay Fault

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Statistically estimating path delay fault coverage in combinational circuits

IEEE Pacific Rim Conference on Communications, Computers, and Signal Processing. Proceedings ◽

10.1109/pacrim.1995.519569 ◽

2002 ◽

Cited By ~ 1

Author(s):

Z. Zhang ◽

R.D. McLeod ◽

D.M. Miller ◽

S. Zhang

Keyword(s):

Fault Coverage ◽

Path Delay ◽

Combinational Circuits ◽

Delay Fault ◽

Path Delay Fault

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Path delay fault diagnosis in combinational circuits with implicit fault enumeration

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.952739 ◽

2001 ◽

Vol 20 (10) ◽

pp. 1226-1235 ◽

Cited By ~ 20

Author(s):

P. Pant ◽

Yuan-Chieh Hsu ◽

S.K. Gupta ◽

A. Chatterjee

Keyword(s):

Fault Diagnosis ◽

Path Delay ◽

Combinational Circuits ◽

Delay Fault ◽

Path Delay Fault

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An efficient nonenumerative method to estimate the path delay fault coverage in combinational circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.259947 ◽

1994 ◽

Vol 13 (2) ◽

pp. 240-250 ◽

Cited By ~ 37

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Fault Coverage ◽

Path Delay ◽

Combinational Circuits ◽

Delay Fault ◽

Path Delay Fault

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Resynthesis of combinational circuits for path count reduction and for path delay fault testability

Proceedings ED&TC European Design and Test Conference ◽

10.1109/edtc.1996.494345 ◽

2002 ◽

Cited By ~ 10

Author(s):

A. Krstic ◽

Kwang-Ting Cheng

Keyword(s):

Path Delay ◽

Combinational Circuits ◽

Delay Fault ◽

Path Delay Fault

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Synthesis of multi-level combinational circuits for complete robust path delay fault testability

[1992] Digest of Papers. FTCS-22: The Twenty-Second International Symposium on Fault-Tolerant Computing ◽

10.1109/ftcs.1992.243573 ◽

2003 ◽

Cited By ~ 23

Author(s):

N.H. Jha ◽

I. Pomeranz ◽

S.M. Reddy ◽

R.I. Miller

Keyword(s):

Path Delay ◽

Combinational Circuits ◽

Delay Fault ◽

Path Delay Fault ◽

Multi Level

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On Designing Robust Path-Delay Fault Testable Combinational Circuits Based on Functional Properties

2014 IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2014.81 ◽

2014 ◽

Author(s):

Rupali Mitra ◽

Debesh K. Das ◽

Bhargab B. Bhattacharya

Keyword(s):

Functional Properties ◽

Path Delay ◽

Combinational Circuits ◽

Delay Fault ◽

Path Delay Fault

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