path delay fault testing Latest Research Papers

Cost Effective Adaptive Voltage Scaling Using Path Delay Fault Testing

2018 IEEE East-West Design & Test Symposium (EWDTS) ◽

10.1109/ewdts.2018.8524693 ◽

2018 ◽

Author(s):

Mahroo Zandrahimi ◽

Philippe Debaud ◽

Armand Castillejo ◽

Zaid Al-Ars

Keyword(s):

Cost Effective ◽

Voltage Scaling ◽

Path Delay ◽

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

Path Delay Fault ◽

Path Delay Fault Testing

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Test Sets for Robust Path Delay Fault Testing on Two-Rail Logic Circuits

IEEE Transactions on Computers ◽

10.1109/tc.2010.230 ◽

2011 ◽

Vol 60 (10) ◽

pp. 1459-1470 ◽

Cited By ~ 2

Author(s):

Kazuteru Namba ◽

Hideo Ito

Keyword(s):

Logic Circuits ◽

Path Delay ◽

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

Path Delay Fault ◽

Test Sets ◽

Path Delay Fault Testing

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Path-Delay Fault Testing in Embedded Content Addressable Memories

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools ◽

10.1109/dsd.2010.48 ◽

2010 ◽

Cited By ~ 1

Author(s):

P. Manikandan ◽

Bjorn B. Larsen ◽

Einar J. Aas

Keyword(s):

Path Delay ◽

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

Path Delay Fault ◽

Content Addressable Memories ◽

Path Delay Fault Testing

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Experiments with ABIST test methodology applied to path delay fault testing

2010 East-West Design & Test Symposium (EWDTS) ◽

10.1109/ewdts.2010.5742129 ◽

2010 ◽

Cited By ~ 1

Author(s):

P. Manikandan ◽

Bjorn B. Larsen ◽

Einar J. Aas

Keyword(s):

Path Delay ◽

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

Test Methodology ◽

Path Delay Fault ◽

Path Delay Fault Testing

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Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding

IEICE Transactions on Information and Systems ◽

10.1587/transinf.e92.d.269 ◽

2009 ◽

Vol E92-D (2) ◽

pp. 269-282 ◽

Cited By ~ 1

Author(s):

Kazuteru NAMBA ◽

Hideo ITO

Keyword(s):

Path Delay ◽

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

Test Compression ◽

Path Delay Fault ◽

Path Delay Fault Testing ◽

Statistical Coding

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Tri-scan: a novel DFT technique for CMOS path delay fault testing

2004 International Conferce on Test ◽

10.1109/test.2004.1387386 ◽

2005 ◽

Cited By ~ 9

Author(s):

R. Datta ◽

Ravi Gupta ◽

A. Sebastine ◽

J.A. Abraham ◽

M. d'Abreu

Keyword(s):

Path Delay ◽

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

Path Delay Fault ◽

Path Delay Fault Testing

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Path delay fault testing of Benes multistage interconnection networks

ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357) ◽

10.1109/icecs.1999.813425 ◽

2003 ◽

Author(s):

H.T. Vergos ◽

M. Bellos ◽

D. Nikolos

Keyword(s):

Interconnection Networks ◽

Path Delay ◽

Fault Testing ◽

Multistage Interconnection Networks ◽

Delay Fault ◽

Delay Fault Testing ◽

Path Delay Fault ◽

Path Delay Fault Testing

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A flexible path selection procedure for path delay fault testing

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) ◽

10.1109/vtest.1999.766659 ◽

2003 ◽

Cited By ~ 5

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Selection Procedure ◽

Path Selection ◽

Path Delay ◽

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

Path Delay Fault ◽

Path Delay Fault Testing

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On path delay fault testing of multiplexer-based shifters

Proceedings Ninth Great Lakes Symposium on VLSI ◽

10.1109/glsv.1999.757368 ◽

2003 ◽

Author(s):

H.T. Vergos ◽

Y. Tsiatouhas ◽

T. Haniotakis ◽

D. Nikolos ◽

M. Nicolaidis

Keyword(s):

Path Delay ◽

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

Path Delay Fault ◽

Path Delay Fault Testing

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Path delay fault testing of ICs with embedded intellectual property blocks

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) ◽

10.1109/date.1999.761105 ◽

2003 ◽

Cited By ~ 2

Author(s):

D. Nikolos ◽

T. Haniotakis ◽

H.T. Vergos ◽

Y. Tsiatouhas

Keyword(s):

Intellectual Property ◽

Path Delay ◽

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

Path Delay Fault ◽

Path Delay Fault Testing

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path delay fault testing
Recently Published Documents

TOTAL DOCUMENTS

H-INDEX

Cost Effective Adaptive Voltage Scaling Using Path Delay Fault Testing

Test Sets for Robust Path Delay Fault Testing on Two-Rail Logic Circuits

Path-Delay Fault Testing in Embedded Content Addressable Memories

Experiments with ABIST test methodology applied to path delay fault testing

Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding

Tri-scan: a novel DFT technique for CMOS path delay fault testing

Path delay fault testing of Benes multistage interconnection networks

A flexible path selection procedure for path delay fault testing

On path delay fault testing of multiplexer-based shifters

Path delay fault testing of ICs with embedded intellectual property blocks

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path delay fault testingRecently Published Documents

TOTAL DOCUMENTS

H-INDEX

Cost Effective Adaptive Voltage Scaling Using Path Delay Fault Testing

Test Sets for Robust Path Delay Fault Testing on Two-Rail Logic Circuits

Path-Delay Fault Testing in Embedded Content Addressable Memories

Experiments with ABIST test methodology applied to path delay fault testing

Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding

Tri-scan: a novel DFT technique for CMOS path delay fault testing

Path delay fault testing of Benes multistage interconnection networks

A flexible path selection procedure for path delay fault testing

On path delay fault testing of multiplexer-based shifters

Path delay fault testing of ICs with embedded intellectual property blocks

path delay fault testing
Recently Published Documents