New Measurement Method for Self-Heating in Silicon-on-Insulator MOSFETs Based on Shared Series Resistance

2020 ◽  
Vol 41 (2) ◽  
pp. 212-215
Author(s):  
Wangyong Chen ◽  
Linlin Cai ◽  
Yongfeng Cao ◽  
Duanquan Liao ◽  
Ming Tian ◽  
...  
Keyword(s):  
Measurement Method ◽  
Series Resistance ◽  
Silicon On Insulator ◽  
Self Heating

Behavior of contact-silicided TFSOI gate structures

1994 ◽  
Vol 52 ◽  
pp. 860-861
Author(s):  
N. David Theodore ◽  
Juergen Foerstner ◽  
Peter Fejes
Keyword(s):  
Semiconductor Device ◽  
Series Resistance ◽  
Field Effect Transistors ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
Continuous Layer ◽  
Buried Oxide ◽  
Device Structures ◽  
Thin Silicon

As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of thin-film silicon-on-insulator (TFSOI) substrates for device fabrication is being explored in order to increase switching speeds. One version of TFSOI being explored for device fabrication is SIMOX (Silicon-separation by Implanted OXygen).A buried oxide layer is created by highdose oxygen implantation into silicon wafers followed by annealing to cause coalescence of oxide regions into a continuous layer. A thin silicon layer remains above the buried oxide (~220 nm Si after additional thinning). Device structures can now be fabricated upon this thin silicon layer.Current fabrication of metal-oxidesemiconductor field-effect transistors (MOSFETs) requires formation of a polysilicon/oxide gate between source and drain regions. Contact to the source/drain and gate regions is typically made by use of TiSi2 layers followedby Al(Cu) metal lines. TiSi2 has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions

Silicidation Strategy Of Sub-0.1 μm Junctions for Deep Submicron Devices

1995 ◽  
Vol 402 ◽  
Author(s):  
Jiunn-Yann Tsai ◽  
Carlton M. Osburn ◽  
Steve L. Hsia
Keyword(s):  
Series Resistance ◽  
Deep Submicron ◽  
Silicon On Insulator ◽  
Promising Alternative ◽  
Resistance Increase ◽  
Low Leakage ◽  
Submicron Devices ◽  
Diffusion Source ◽  
Ultra Shallow Junctions ◽  
Silicon Interface

AbstractTwo major concerns for silicidation of ultra-shallow junctions, namely the silicon-consumption- induced junction leakage and the series resistance increase, were compared among conventional post-junction-silicide (PJS) contact, silicide-as-a-diffusion-source (SADS) contact, Silicon-On-Insulator (SOI) contact, and elevated-source-drain (ESD) contact. Even though we found that ESD contacts would be the ultimate solution for both problems, SOI and SADS contacts provide better resistance to silicon-consumption-induced series resistance increase over conventional PJS contact because both are able to maintain a high dopant concentration at the silicide/silicon interface and thus a low specific contact resistivity. While there is no junction leakage concern for SOI contact, the SADS junction is also distinguished by low leakage owing to its lack of implant damage in the silicon substrate and uniformly doped junction along the silicide/silicon interface contour. MOSFET devices with SADS source/drain were demonstrated with quarter-μm technology. Epitaxial cobalt disilicide (CoSi2) was formed using the Ti/Co bilayer technique as a diffusion source. While both ESD and SOI processes still suffer from process complexity, integration and materials issues, we conclude that SADS contacting is a promising alternative for deep submicron devices.

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