Self-heating as a tool for measuring sub-0.1-μm silicon-on-insulator device parameters

1998 ◽  
Author(s):  
Mohamed A. Osman ◽  
Ashraf A. Osman
Keyword(s):  
Silicon On Insulator ◽  
Self Heating

New Measurement Method for Self-Heating in Silicon-on-Insulator MOSFETs Based on Shared Series Resistance

2020 ◽  
Vol 41 (2) ◽  
pp. 212-215
Author(s):  
Wangyong Chen ◽  
Linlin Cai ◽  
Yongfeng Cao ◽  
Duanquan Liao ◽  
Ming Tian ◽  
...  
Keyword(s):  
Measurement Method ◽  
Series Resistance ◽  
Silicon On Insulator ◽  
Self Heating

scholarly journals A Proposal of Vertical MOSFET and Electrothermal Analysis for Monolithic 3-D ICs

Electronics ◽  
2021 ◽  
Vol 10 (18) ◽  
pp. 2241
Author(s):  
Jia-He Zhu ◽  
Da-Wei Wang ◽  
Wen-Sheng Zhao ◽  
Jia-Yun Dai ◽  
Gaofeng Wang
Keyword(s):  
Power Consumption ◽  
Leakage Current ◽  
Pulse Current ◽  
Critical Factor ◽  
Silicon On Insulator ◽  
The Self ◽  
Heating Effect ◽  
Saturation Current ◽  
Current Ratio ◽  
Self Heating

In this paper, an innovative vertical MOSFET based on through-oxide via (TOV) technology is proposed for silicon-on-insulator (SOI)-based monolithic 3-D ICs. The proposed vertical MOSFET is investigated numerically. It was found that SOI can effectively reduce the parasitic capacitance, leakage current, power consumption, as well as suppress the pulse current interference of the substrate. The simulated results indicate that the proposed MOSFET possesses excellent characteristics in saturation current over 1500 μA, sub-threshold swing of 69 mV/dec, and on/off current ratio of 1.28 × 1011. Moreover, as temperature is a critical factor for the performance degradation of semiconductor devices, electrothermal simulations are conducted to predict the influence of the self-heating effect on device characteristics. The results show that device characteristics slightly deteriorate, but can still acceptable in their applications.

Improvement in Self-Heating Characteristic by Utilizing Sapphire Substrate in Omega-Gate-Shaped Nanowire Field Effect Transistor for Wearable, Military, and Aerospace Application

2021 ◽  
Vol 21 (5) ◽  
pp. 3092-3098
Author(s):  
Young Suh Song ◽  
Hyunwoo Kim ◽  
Junsu Yu ◽  
Jongho Lee
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Heat Dissipation ◽  
Silicon On Insulator ◽  
The Self ◽  
Self Heating ◽  
Aerospace Applications ◽  
Radiation Resistant ◽  
Effect Transistor

In this study, we propose an omega-shaped-gate nanowire field effect transistor (ONWFET) with a silicon-on-sapphire (SOS) substrate. In order to investigate improvements in the self-heating characteristic with the use of a SOS substrate, the lattice temperature is examined using a Synopsys Sentaurus 3D Technology computer-aided design (TCAD) simulator with the results compared to those with a silicon-on-insulator (SOI) substrate. To validate the proposed structure with the SOS substrate, the locations of hot spots and heat dissipation paths (heat sinks) depending on the substrate materials are also analyzed. The electrical characteristics, specifically the on-current (Ion), off-current (Ioff), and subthreshold swing (SS), were investigated as well. Hence, it is demonstrated here that incorporating a SOS substrate can improve both the self-heating characteristic and the SS at the same time. Therefore, enhanced logic devices are feasible if using an ONWFET with a SOS substrate. Examples include wearable devices and military and future aerospace applications achieved by the radiation-resistant material Al2O3 that has high thermal conductivity.

scholarly journals Influence of Self-Heating Effect on I-V Dates of Party Depleted Submicron Silicon-on-Insulator CMOS Transistors at High Ambient Temperatures

2019 ◽  
Vol 9 (1) ◽  
pp. 1446-1450
Keyword(s):  
High Temperature ◽  
Ambient Temperature ◽  
Silicon On Insulator ◽  
The Self ◽  
Heating Effect ◽  
Self Heating ◽  
Cmos Transistors ◽  
Cmos Transistor ◽  
Supply Voltages ◽  
Soi Cmos

To solve the problems of high temperature microelectronics the influence of the self heating effect on the IV dates partially depleted submicron silicon–on-insulator CMOS transistor in the ambient temperature range from 525 K to 650 K is discussed. Approach consists in combination of experimental data and of computational simulating results. For simulation of electrothermal characteristics of SOI CMOS transistor is considered three-layered structure. Temperature distribution is calculated numerically using iterative algorithm in conjunction with software COMSOL Multiphysics. I-V dates of SOI CMOS transistors are calculated by means of two-dimensional models for n-and p-channel transistors of Sentaurus TCAD developed in the system of instrument and technological modelling. TCAD models are calibrated on experimental characteristics for 525 K. It is shown that with growth of ambient temperature the selfheating mechanism contribution consistently decreases. By results of modeling it is established that self-heating contributions at supply voltages 5.5 V to decreases for ntransistor in 2.8 times, p-transistor in 2.2 times. The relative decline of current n-type transistor for reduced from 11.6% to 5.5% and for p-type with 15% to 9%. However, different dynamics of current recession for n-and p-transistors is significant for analog applications that need to be considered at high-temperature circuit design. The proposed methodology allows to critically assess the contribution of the self-heating mechanism on the I-V dates for a wide range of high temperatures and supply voltages. Underestimating this fact leads to unreasonable values for the maximum temperature and limit of thermal stability for the separate SOI CMOS transistor. In total this can be a prerequisite for a significant simplification of the design of not only the chip construction but also the whole electronic Board.

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