Low-voltage DRAM sensing scheme with offset-cancellation sense amplifier

2002 ◽  
Vol 37 (10) ◽  
pp. 1356-1360 ◽  
Author(s):  
Sanghoon Hong ◽  
Sejun Kim ◽  
Jae-Kyung Wee ◽  
Seongsoo Lee
2005 ◽  
Vol 40 (2) ◽  
pp. 507-514 ◽  
Author(s):  
A. Conte ◽  
G.L. Giudice ◽  
G. Palumbo ◽  
A. Signorello

Electronics ◽  
2020 ◽  
Vol 9 (9) ◽  
pp. 1403 ◽  
Author(s):  
Taehui Na

With technology scaling, achieving a target read yield of resistive nonvolatile memories becomes more difficult due to increased process variation and decreased supply voltage. Recently, an offset-canceling dual-stage sensing circuit (OCDS-SC) has been proposed to improve the read yield by canceling the offset voltage and utilizing a double-sensing-margin structure. In this paper, an offset-canceling zero-sensing-dead-zone sense amplifier (OCZS-SA) combined with the OCDS-SC is proposed to significantly improve the read yield. The OCZS-SA has two major advantages, namely, offset voltage cancellation and a zero sensing dead zone. The Monte Carlo HSPICE simulation results using a 65-nm predictive technology model show that the OCZS-SA achieves 2.1 times smaller offset voltage with a zero sensing dead zone than the conventional latch-type SAs at the cost of an increased area overhead of 1.0% for a subarray size of 128 × 16.


2015 ◽  
Vol 62 (7) ◽  
pp. 1776-1784 ◽  
Author(s):  
Byungkyu Song ◽  
Taehui Na ◽  
Jisu Kim ◽  
Jung Pill Kim ◽  
Seung H. Kang ◽  
...  

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