2016 20th International Symposium on VLSI Design and Test (VDAT)
Latest Publications

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9781509014224

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A FSM based approach for efficient implementation of K-means algorithm

2016 20th International Symposium on VLSI Design and Test (VDAT) ◽

10.1109/isvdat.2016.8064848 ◽

2016 ◽

Cited By ~ 4

Author(s):

Rahul Ratnakumar ◽

Satyasai Jagannath Nanda

Keyword(s):

Efficient Implementation

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A Pre-RTL floorplanner tool for automated CMP design space exploration with thermal awareness

2016 20th International Symposium on VLSI Design and Test (VDAT) ◽

10.1109/isvdat.2016.8064876 ◽

2016 ◽

Cited By ~ 1

Author(s):

Sri Harsha Gade ◽

Praveen Kumar ◽

Sujay Deb

Keyword(s):

Design Space Exploration ◽

Design Space ◽

Space Exploration

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Golden IC free methodology for hardware Trojan detection using symmetric path delays

2016 20th International Symposium on VLSI Design and Test (VDAT) ◽

10.1109/isvdat.2016.8064895 ◽

2016 ◽

Cited By ~ 2

Author(s):

Ramakrishna Vaikuntapu ◽

Lava Bhargava ◽

Vineet Sahula

Keyword(s):

Hardware Trojan ◽

Hardware Trojan Detection ◽

Trojan Detection

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Message from the general chairs

2016 20th International Symposium on VLSI Design and Test (VDAT) ◽

10.1109/isvdat.2016.8064833 ◽

2016 ◽

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An area and performance aware ECG encoder design for wireless healthcare services

2016 20th International Symposium on VLSI Design and Test (VDAT) ◽

10.1109/isvdat.2016.8064861 ◽

2016 ◽

Author(s):

Bharat Garg ◽

Sameer Yadav ◽

G K Sharma

Keyword(s):

Healthcare Services ◽

And Performance

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Variability and reliability aware surrogate model for sensing delay analysis of SRAM sense amplifier

2016 20th International Symposium on VLSI Design and Test (VDAT) ◽

10.1109/isvdat.2016.8064839 ◽

2016 ◽

Author(s):

Sapna Khandelwal ◽

Jyoti Meena ◽

Lokesh Garg ◽

Dharmendar Boolchandani

Keyword(s):

Surrogate Model ◽

Delay Analysis ◽

Sense Amplifier

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A unified Verilog-A compact model for lateral Si nanowire (NW) FET incorporating parasitics for circuit simulation

2016 20th International Symposium on VLSI Design and Test (VDAT) ◽

10.1109/isvdat.2016.8064852 ◽

2016 ◽

Cited By ~ 2

Author(s):

Om. Prakash ◽

S. Maheshwaram ◽

M. Sharma ◽

A. Bulusu ◽

A. K. Saxena ◽

...

Keyword(s):

Circuit Simulation ◽

Compact Model ◽

Si Nanowire

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List of sub-reviewers

2016 20th International Symposium on VLSI Design and Test (VDAT) ◽

10.1109/isvdat.2016.8064837 ◽

2016 ◽

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Formal verification of switched capacitor DC to DC power converter using circuit simulation traces

2016 20th International Symposium on VLSI Design and Test (VDAT) ◽

10.1109/isvdat.2016.8064894 ◽

2016 ◽

Author(s):

Ambuj Mishra ◽

Subir K Roy

Keyword(s):

Formal Verification ◽

Circuit Simulation ◽

Power Converter ◽

Switched Capacitor ◽

Dc Power

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Planning based guided reconstruction of corner cases in architectural validation

2016 20th International Symposium on VLSI Design and Test (VDAT) ◽

10.1109/isvdat.2016.8064887 ◽

2016 ◽

Author(s):

Rajib Lochan Jana ◽

Shashank Kuchibhotla ◽

Soumyajit Dey ◽

Pallab Dasgupta ◽

Rakesh Kumar

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2016 20th International Symposium on VLSI Design and Test (VDAT)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

A FSM based approach for efficient implementation of K-means algorithm

A Pre-RTL floorplanner tool for automated CMP design space exploration with thermal awareness

Golden IC free methodology for hardware Trojan detection using symmetric path delays

Message from the general chairs

An area and performance aware ECG encoder design for wireless healthcare services

Variability and reliability aware surrogate model for sensing delay analysis of SRAM sense amplifier

A unified Verilog-A compact model for lateral Si nanowire (NW) FET incorporating parasitics for circuit simulation

List of sub-reviewers

Formal verification of switched capacitor DC to DC power converter using circuit simulation traces

Planning based guided reconstruction of corner cases in architectural validation

2016 20th International Symposium on VLSI Design and Test (VDAT)
Latest Publications