A high speed low voltage latch type sense amplifier for non-volatile memory

Author(s):  
Disha Arora ◽  
Anil K. Gundu ◽  
Mohammad S. Hashmi
1998 ◽  
Vol 19 (1-4) ◽  
pp. 159-177 ◽  
Author(s):  
S. Aggarwal ◽  
A. S. Prakash ◽  
T. K. Song ◽  
S. Sadashivan ◽  
A. M. Dhote ◽  
...  

2021 ◽  
Vol 17 (3) ◽  
pp. 1-25
Author(s):  
Bohong Zhu ◽  
Youmin Chen ◽  
Qing Wang ◽  
Youyou Lu ◽  
Jiwu Shu

Non-volatile memory and remote direct memory access (RDMA) provide extremely high performance in storage and network hardware. However, existing distributed file systems strictly isolate file system and network layers, and the heavy layered software designs leave high-speed hardware under-exploited. In this article, we propose an RDMA-enabled distributed persistent memory file system, Octopus + , to redesign file system internal mechanisms by closely coupling non-volatile memory and RDMA features. For data operations, Octopus + directly accesses a shared persistent memory pool to reduce memory copying overhead, and actively fetches and pushes data all in clients to rebalance the load between the server and network. For metadata operations, Octopus + introduces self-identified remote procedure calls for immediate notification between file systems and networking, and an efficient distributed transaction mechanism for consistency. Octopus + is enabled with replication feature to provide better availability. Evaluations on Intel Optane DC Persistent Memory Modules show that Octopus + achieves nearly the raw bandwidth for large I/Os and orders of magnitude better performance than existing distributed file systems.


2010 ◽  
Vol 21 (24) ◽  
pp. 245201 ◽  
Author(s):  
Shiqian Yang ◽  
Qin Wang ◽  
Manhong Zhang ◽  
Shibing Long ◽  
Jing Liu ◽  
...  

2003 ◽  
Author(s):  
N. Matsuzaki ◽  
T. Ishimaru ◽  
Y. Okuyama ◽  
T. Mine ◽  
H. Kume ◽  
...  

2014 ◽  
Vol 114 ◽  
pp. 22-25 ◽  
Author(s):  
M.A. García-Ramírez ◽  
A.M. Ghiass ◽  
Z. Moktadir ◽  
Y. Tsuchiya ◽  
H. Mizuta

IEEE Access ◽  
2020 ◽  
Vol 8 ◽  
pp. 21857-21865 ◽  
Author(s):  
Kang-Un Choi ◽  
Seungbum Baek ◽  
Jino Heo ◽  
Jong-Phil Hong

2022 ◽  
Vol 27 (2) ◽  
pp. 1-18
Author(s):  
Shaahin Angizi ◽  
Navid Khoshavi ◽  
Andrew Marshall ◽  
Peter Dowben ◽  
Deliang Fan

Magneto-Electric FET ( MEFET ) is a recently developed post-CMOS FET, which offers intriguing characteristics for high-speed and low-power design in both logic and memory applications. In this article, we present MeF-RAM , a non-volatile cache memory design based on 2-Transistor-1-MEFET ( 2T1M ) memory bit-cell with separate read and write paths. We show that with proper co-design across MEFET device, memory cell circuit, and array architecture, MeF-RAM is a promising candidate for fast non-volatile memory ( NVM ). To evaluate its cache performance in the memory system, we, for the first time, build a device-to-architecture cross-layer evaluation framework to quantitatively analyze and benchmark the MeF-RAM design with other memory technologies, including both volatile memory (i.e., SRAM, eDRAM) and other popular non-volatile emerging memory (i.e., ReRAM, STT-MRAM, and SOT-MRAM). The experiment results for the PARSEC benchmark suite indicate that, as an L2 cache memory, MeF-RAM reduces Energy Area Latency ( EAT ) product on average by ~98% and ~70% compared with typical 6T-SRAM and 2T1R SOT-MRAM counterparts, respectively.


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