A rail-to-rail low-power latch comparator with time domain bulk-tuned offset cancellation for low-voltage applications

2018 ◽  
Vol 46 (11) ◽  
pp. 1968-1984 ◽  
Author(s):  
Nima Shahpari ◽  
Mehdi Habibi
Keyword(s):  
Low Power ◽  
Time Domain ◽  
Low Voltage ◽  
Offset Cancellation ◽  
Rail To Rail

scholarly journals A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

2021 ◽  
Vol 11 (2) ◽  
pp. 19
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Process ◽  
Slew Rate ◽  
Large Signal ◽  
Output Stage ◽  
Ultra Low Power ◽  
Input Stage ◽  
Rail To Rail

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

scholarly journals A 2.5 Gbps, 10-Lane, Low-Power, LVDS Transceiver in 28 nm CMOS Technology

Electronics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 350 ◽  
Author(s):  
Xu Bai ◽  
Jianzhong Zhao ◽  
Shi Zuo ◽  
Yumei Zhou
Keyword(s):  
Low Power ◽  
High Speed ◽  
Low Voltage ◽  
Cmos Technology ◽  
Common Mode ◽  
Serial Interface ◽  
Common Mode Voltage ◽  
Rail To Rail ◽  
The Common ◽  
28 Nm

This paper presents a 2.5 Gbps 10-lane low-power low voltage differential signaling (LVDS) transceiver for a high-speed serial interface. In the transmitter, a complementary MOS H-bridge output driver with a common mode feedback (CMFB) circuit was used to achieve a stipulated common mode voltage over process, voltage and temperature (PVT) variations. The receiver was composed of a pre-stage common mode voltage shifter and a rail-to-rail comparator. The common mode voltage shifter with an error amplifier shifted the common mode voltage of the input signal to the required range, thereby the following rail-to-rail comparator obtained the maximum transconductance to recover the signal. The chip was fabricated using SMIC 28 nm CMOS technology, and had an area of 1.46 mm2. The measured results showed that the output swing of the transmitter was around 350 mV, with a root-mean-square (RMS) jitter of 3.65 [email protected] Gbps, and the power consumption of each lane was 16.51 mW under a 1.8 V power supply.

Low-Voltage Low-Power CMOS Rail-to-Rail Voltage-to-Current Converters

2013 ◽  
Vol 60 (9) ◽  
pp. 2333-2342 ◽  
Author(s):  
Cristina Azcona ◽  
Belen Calvo ◽  
Santiago Celma ◽  
Nicolas Medrano ◽  
Pedro A. Martinez
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Rail To Rail ◽  
Low Power Cmos

scholarly journals A Low-Power, High-Gain Amplifier with Rail-to-Rail Operating Capability: Applications to Biomedical Signal Processing

2021 ◽  
Vol 58 (1) ◽  
pp. 71-76
Author(s):  
Hassan Faraji Baghtash ◽  
Rasoul Pakdel
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Process Variations ◽  
High Gain ◽  
Biomedical Signal Processing ◽  
Noise Power ◽  
Well Performance ◽  
Subthreshold Region ◽  
Rail To Rail ◽  
Unity Gain

low-voltage, low-power, rail-to-rail, two-stage trans-conductance amplifier is presented. The structure exploits body-driven transistors, configured in folded-cascode structure. To reduce the power consumption, the transistors are biased in the subthreshold region. The Specter RF simulation results which are conducted in TSMC 180nm CMOS standard process proves the well-performance of the proposed structure. The performance of the proposed structure against process variations is checked through process corners and Monte Carlo simulations. The results prove the robustness of the proposed amplifier against process uncertainties. Some important specifications of the design derived from circuit simulations are 93.36 dB small-signal gain, 14.4 PV2/Hz input referred noise power, 26.5 kHz unity gain frequency, 20 V/ms slew rate. The proposed structure draws 260 nW power from 0.5 V power supply and is loaded with a 15 pF loading capacitor. The input common mode range of structure is from 0 to 0.5 V.

Low power time-domain rail-to-rail comparator with a new delay element for ADC applications

Integration ◽  
2021 ◽  
Vol 77 ◽  
pp. 89-95
Author(s):  
Roohollah Sanati ◽  
Farzan Khatib ◽  
Mohammad Javadian Sarraf ◽  
Reihaneh Kardehi Moghaddam
Keyword(s):  
Low Power ◽  
Time Domain ◽  
Delay Element ◽  
Rail To Rail
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