High-Density Through Silicon Vias for 3-D LSIs

2009 ◽  
Vol 97 (1) ◽  
pp. 49-59 ◽  
Author(s):  
Mitsumasa Koyanagi ◽  
Takafumi Fukushima ◽  
Tetsu Tanaka
Keyword(s):  
High Density ◽  
Through Silicon Vias ◽  
Silicon Vias

scholarly journals Characterization of high density through silicon vias with spectral reflectometry

2011 ◽  
Vol 19 (7) ◽  
pp. 5993 ◽  
Author(s):  
Yi-Sha Ku ◽  
Kuo Cheng Huang ◽  
Weite Hsu
Keyword(s):  
High Density ◽  
Through Silicon Vias ◽  
Silicon Vias

CMOS-Compatible Through Silicon Vias for 3D Process Integration

2006 ◽  
Vol 970 ◽  
Author(s):  
Cornelia K. Tsang ◽  
Paul S. Andry ◽  
Edmund J. Sprogis ◽  
Chirag S. Patel ◽  
Bucknell C. Webb ◽  
...  
Keyword(s):  
Mechanical Stability ◽  
Process Integration ◽  
Three Dimensional ◽  
High Density ◽  
High Yield ◽  
Large Area ◽  
Process Flow ◽  
Through Silicon Via ◽  
Through Silicon Vias ◽  
Silicon Vias

ABSTRACTAs the limits of traditional CMOS scaling are approached, process integration has become increasingly difficult and resulting in a diminished rate of performance improvement over time. Consequently, the search for new two- and three- dimensional sub-system solutions has been pursued. One such solution is a silicon carrier-based System-on-Package (SOP) that enables high-density interconnection of heterogeneous die beyond current first level packaging densities. Silicon carrier packaging contains through silicon vias (TSV), fine pitch Cu wiring and high-density solder pads/joins, all of which are compatible with traditional semiconductor methods and tools. These same technology elements, especially the through silicon via process, also enable three dimensional stacking and integration. An approach to fabricating electrical through-vias in silicon is described, featuring annular-shaped vias instead of the more conventional cylindrical via. This difference enables large-area, uniform arrays to be produced with high yield as it is simpler to integrate into a conventional CMOS back-end-of-line (BEOL) process flow. Furthermore, the CTE-matched silicon core provides improved mechanical stability and the dimensions of the annular via allows for metallization by various means including copper electroplating or CVD tungsten deposition. An annular metal conductor process flow will be described. Through-via resistance measurements of 50, 90, and 150μm deep tungsten-filled annular vias will be compared. Two silicon carrier test vehicle designs, containing more than 2,200 and 9,600 electrical through-vias, respectively, were built to determine process yield and uniformity of via resistance. Through silicon via resistances range from 15-40 mΩ, and yields in excess of 99.99% have been demonstrated.

RF characterization and modelling of high density Through Silicon Vias for 3D chip stacking

2010 ◽  
Vol 87 (3) ◽  
pp. 491-495 ◽  
Author(s):  
L. Cadix ◽  
C. Bermond ◽  
C. Fuchs ◽  
A. Farcy ◽  
P. Leduc ◽  
...  
Keyword(s):  
High Density ◽  
Through Silicon Vias ◽  
Silicon Vias ◽  
3D Chip Stacking

Advanced Silicon Interposer for High density and High Integration Electronic Packages

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 000865-000905
Author(s):  
SATORU KUMOCHI ◽  
Sumio Koiwa ◽  
Kosuke Suzuki ◽  
Yoshitaka Fukuoka
Keyword(s):  
System Integration ◽  
High Density ◽  
High Resistivity ◽  
Through Silicon Vias ◽  
Passive Device ◽  
Fine Pitch ◽  
Mems Technology ◽  
Cte Mismatch ◽  
Silicon Vias ◽  
Electrical Loss

As electronic product becomes smaller and lighter with an increasing number of function← the demand for high density and high integration becomes stronger. Interposers for system in package will became more and more important for advanced electronic systems. Interposers will be needed more complicated structure for 2.5D , 3D package and MEMS, OEMEMS new heterogeneous package structure Silicon interposers with through silicon vias (TSV) and back end of line (BEOL) wirring offer compelling benefits for 2.5D and 3D system integration; however, they are limited by high cost and high electrical loss. [1] This paper presents the demonstration of Silicon Interposers with fine pitch through Silicon vias(TSV),with embedded passive device. We have developed the TSV interposer with redistribution layers on both sides using MEMS technology, high aspect ratio deep etching technology and filled Cu plating with deep through holes for cost reduction and low electrical loss. The TSV interposer with 400μm thick high resistivity Si, obtained without backside processing use of carriers. Excellent through via reliability was demonstrated, due to double side thick polymer insulator that buffers the stress created by CTE mismatch between glass, copper vias and copper traces, and TSV at 200μm pitch passed 1000 thermal cycles from −55°C to 125°C. We have evaluated high frequency transmission characteristic of Si through hole by the measurement S21 parameter. Highly insulating TSV resulted in insertion loss of less than 1dB at 20GHz. Thin film SiN capacitor as embedded passive device was built in surface of TSV interposer by via first and via last method. The capacitance and leakage current of capacitor was measured and compared with two types of fabrication method.

Innovative polyimide liner deposition method for high-aspect-ratio and high-density through-silicon-vias (TSVs)

2016 ◽  
Vol 149 ◽  
pp. 78-84 ◽  
Author(s):  
Yingtao Ding ◽  
Miao Xiong ◽  
Yangyang Yan ◽  
Shiwei Wang ◽  
Qianwen Chen ◽  
...  
Keyword(s):  
Aspect Ratio ◽  
High Aspect Ratio ◽  
High Density ◽  
Deposition Method ◽  
Through Silicon Vias ◽  
Silicon Vias
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