scholarly journals Design a scalable ethernet Network Interface supporting the Large Receive Offload

2012 ◽  
Author(s):  
Mohamed Elbeshti ◽  
Mike Dixon ◽  
Terry Koziniec
Keyword(s):  
Network Interface ◽  
Ethernet Network

On an Internet Interface in an Embedded POS System for Internet of Things

2010 ◽  
Vol 44-47 ◽  
pp. 3333-3337
Author(s):  
Ye Xu ◽  
Hai Zhao
Keyword(s):  
Internet Of Things ◽  
Low Cost ◽  
Network Interface ◽  
The Internet ◽  
Network Configuration ◽  
Practical Application ◽  
Embedded Platform ◽  
Remote Management ◽  
Ethernet Network ◽  
Simple Network

This paper designs and implements an Internet interface in an embedded POS system based on Webit, an embedded platform and interface for Internet of things which is a self-owned intellectual property of Lab. of Embedded Technology, Northeastern University, China. The Internet interface is designed and implemented on an 8-bit RISC micro-controller and Ethernet Network Interface Controller, with a real-time OS – WebitOS 2.0 strictly conforming to TCP/IP protocol requirements. Then experiments of testing functions and the performance of the embedded POS system are performed. And results show that the POS system based on Webit has a practical application value with properties such as low cost, and capabilities of simple network configuration and remote management.

A Study Using a Risc Core for 100 Gbps Ethernet Network Interfaces

2011 ◽  
Vol 403-408 ◽  
pp. 522-531
Author(s):  
M Elbeshti ◽  
M Dixon
Keyword(s):  
High Performance ◽  
General Purpose ◽  
Network Interface ◽  
Data Movement ◽  
Wide Range ◽  
Movement Type ◽  
Speed Up ◽  
Reduced Costs ◽  
Ethernet Network ◽  
Network Interfaces

The performance of the current and the next generation server applications such as E-Commerce, Storage and Web server that employ TCP/IP and UDP/IP as the communication protocol of choice depends upon the efficiency of the Protocol Stack Processing within this node. As the speed of networks exceeds one GBPS, the design and implementation of high-performance Network Interfaces (NI) for servers become very challenging. It is observed that using programmable NI with a general purpose processing core to offload some of the TCP/IP or UDP/IP protocol functions can deliver some important features which include scalability, short development times and reduced costs. In this paper, we proposes a new NI-programmable based model that support the Large Segment Offload (LSO) for sending side and a novel technique called Receiving Side Amalgamating (RSA) for receiving side and which is used for incoming packets. The core engine assigned to handle these functions is single specialized embedded processors utilizing RISC cores in each side. As a result, a 240 MHz RISC core can be used in Ethernet Network Interface ENI card for wide range of transmission line speed up to 100 Gbps. These results are based on the use of a specialized RISC core that we developed and simulated. Also, the author has discussed some of the design issues that are related to RISC core based NI and the data movement type.

Network interface systems

1976 ◽  
Author(s):  
Joe B. Wyatt ◽  
Vincent I. Polley
Keyword(s):  
Network Interface

scholarly journals The Data Acquisition System of the Na62 Experiment at Cern

2019 ◽  
Vol 214 ◽  
pp. 01037
Author(s):  
Marco Boretto
Keyword(s):  
Data Acquisition ◽  
High Performance ◽  
Branching Ratio ◽  
Data Acquisition System ◽  
Acquisition System ◽  
Trigger System ◽  
Level Trigger ◽  
Decay Products ◽  
Ethernet Network ◽  
Trigger Decision

The aim of the NA62 experiment is to study the extreme rare kaon decay K+ ? π+vv and to measure its branching ratio with a 10% accuracy. In order to do so, a very high intensity beam from the CERN SPS is used to produce charged kaons whose decay products are detected by many detectors installed along a 60 m decay region. The NA62 Data Acquisition system (DAQ) exploits a multi-level trigger system; following a Level0 (L0) trigger decision, 1 MHz data rate from about 60 sources is read by a PC-farm, the partial event is built and then passed through a series of Level1 (L1) algorithms to further reduce the trigger rate. Events passing this level are completed with the missing, larger, data sources (~400 sources) at the rate of 100 KHz. The DAQ is built around a high performance ethernet network interconnecting the detectors to a farm of 30 servers. After an overall description of the system design and the main implementation choices that allowed to reach the required performance and functionality, this paper describes the overall behaviour of the DAQ in the 2017 data taking period. It then concludes with an outlook of possible improvements and upgrades that may be applied to the system in the future.

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