LTCC-Based Highly Integrated SiPM Module with Integrated Liquid Cooling Channels for High Resolution Molecular Imaging

2018 ◽  
Vol 15 (2) ◽  
pp. 86-94 ◽  
Author(s):  
Rainer Dohle ◽  
Ilaria Sacco ◽  
Thomas Rittweg ◽  
Thomas Friedrich ◽  
Gerold Henning ◽  
...  
Keyword(s):  
Magnetic Resonance ◽  
Image Quality ◽  
Low Temperature ◽  
Flip Chip ◽  
Back Side ◽  
Liquid Cooling ◽  
Cooling Channels ◽  
Hybrid Detection ◽  
The Impact ◽  
Ltcc Substrate

We present a very compact hybrid detection module based on an advanced liquid-cooled low temperature cofired ceramic (LTCC) substrate. The double sided hybrid combines 144 photo detectors and four specialized flip chip readout ASICs (Application specific Integrated Circuits) used for the readout of scintillation crystals with application in time-of-flight positron emission tomography (PET) combined with magnetic resonance imaging (MRI). If MRI images and PET images are combined, completely new medical diagnostic and treatment prospects are feasible because the two techniques are complementary and they will offer both anatomical and functional information. One of the biggest challenges is the development of miniaturized detector modules that are highly functional and MRI compatible. Our SiPM (Silicon Photomultiplier) module has an area of 32.8 by 32.0 mm2 and contains 12 × 12 SiPMs in a pitch of 2.5 mm2. The SiPM readout of the 144 channels is performed by four PETA6 ASICs. The LTCC substrate with a 2.1 mm thickness has been manufactured using the most advanced technologies developed at Micro Systems Engineering GmbH To guarantee the manufacturability in serial or mass production, DP951 P2 green tape has been used. For the cooling channels, special technology has been developed by MSE. The liquid cooling channels inside the LTCC substrate provide excellent cooling for the ASICs, the SiPMs, and thermal insulation between ASICs and SiPMs and allow a very compact design of the detector modules, reducing their height by 50% compared with other technical solutions. We can insert a ring of our modules in an existing MR (Magnetic Resonance) scanner. Operating the SiPMs at low temperature improves their performance, reducing the effects of dark count rate and improving image quality. There is no heatsink, heat pipe, or other cooling element attached to the back side of the ASICs. To avoid interference between the PET and MRI system, short signal length is required for minimizing pickup loops and eddy currents. The 12 SiPM arrays with 2 × 6 geometry are wire bonded only at the edges of the SiPMs to the LTCC, enabling the use of nearly the whole detector area for photon detection, which is of paramount importance for excellent image quality. At the opposite side of the substrate, four ASICs with 272 μm bump pitch are flip chip solder assembled to the LTCC substrate including underfilling, and a few SMD (Surface Mount Device) components are mounted. A scintillator crystal array on top of the SiPMs converts gamma rays (511 keV photons produced from positron-electron annihilation) into light. We assume that the LTCC substrates and all components are fully MRI compatible, which is important for the integration of PET with MRI without mutual interference. The paper elucidates the impact of the used technology on the performance of advanced PET/MRI detector modules.

LTCC Based Highly Integrated SiPM Module With Integrated Liquid Cooling Channels for High Resolution Molecular Imaging

2017 ◽  
Vol 2017 (1) ◽  
pp. 000398-000405
Author(s):  
Rainer Dohle ◽  
Ilaria Sacco ◽  
Thomas Rittweg ◽  
Thomas Friedrich ◽  
Gerold Henning ◽  
...  
Keyword(s):  
Magnetic Resonance Imaging ◽  
Positron Emission Tomography ◽  
Magnetic Resonance ◽  
Flip Chip ◽  
Emission Tomography ◽  
Resonance Imaging ◽  
Liquid Cooling ◽  
Cooling Channels ◽  
Positron Emission ◽  
Ltcc Substrate

Abstract We present a very compact hybrid detection module based on an advanced liquid-cooled LTCC substrate. The double sided hybrid combines 144 photo detectors and 4 specialized flip-chip readout ASICs used for the readout of scintillation crystals with application in time-of-flight (TOF) Positron Emission Tomography (PET) combined with Magnetic Resonance Imaging (MRI). Positron Emission Tomography is mostly known for its use in oncology applications, cardiovascular disease, and imaging of brain functions. If MRI images and PET images are combined, completely new medical diagnostic and treatment prospects are feasible since MRI delivers precise anatomical information. One of the biggest challenges is the development of miniaturized detector modules that are highly functional and MRI compatible. Our SiPM module has an area of 32.8 by 32.0 mm2 and contains 12 × 12 SiPMs in a pitch of 2.5 mm2. The SiPM readout of the 144 channels is performed by four PETA6 ASICs. The LTCC substrate with 2.1 mm thickness has been manufactured using the most advanced technologies developed at MSE. In order to guarantee the manufacturability in serial or mass production, DP951 P2 green tape has been used. For the cooling channels, special technology has been developed by MSE. The liquid cooling channels inside the LTCC substrate provide excellent cooling for the ASICs, the SiPMs, and thermal insulation between ASICs and SiPMs and allow a very compact design of the detector modules, reducing their height by 50% compared with other technical solutions. This makes both smaller scanners and larger detector rings possible, the latter being needed for heavier patients. We can insert a ring of our modules in an existing MR scanner. Operating the SiPMs at low temperature improves their performance, reducing the effects of dark count rate and improving image quality. There is no heat sink, heat pipe, or other cooling element attached to the back side of the ASICs. In order to avoid interference between the PET and MRI system, short signal length is required for minimizing pickup loops and eddy currents. The 12 SiPM arrays with 2×6 geometry are wire bonded only at the edges of the SiPMs to the LTCC, enabling the use of nearly the whole detector area for photon detection, which is of paramount importance for excellent image quality. At the opposite side of the substrate, four ASICs with 272 μm bump pitch are flip-chip solder assembled to the LTCC substrate including underfilling, and a few SMD components are mounted. A scintillator crystal array on top of the SiPMs converts gamma-rays (511 keV photons produced from positron-electron annihilation) into light. LTCC substrates and all components are fully MRI compatible, which allows integration of PET with magnetic resonance imaging without mutual interference. The performance of a PET detector is characterized by its time resolution, energy resolution, detection efficiency, and spatial resolution. Each of these factors has a huge influence on the quality of the final PET image. All of these factors are improved with our novel technical solution. With measurements on prototypes, state-of-the-art coincidence time resolution (CTR) for pairs of identical detectors in combination with high spatial resolution have been obtained. The paper elucidates the impact of the employed technology on the performance of advanced PET/MRI detector modules. Novel features of the detector modules will help to enhance the “molecular sensitivity” of PET/MRI scanners.

Backside Sample Preparation Challenges for Fault Localization Analysis of Flip Chip Package

2013 ◽  
Author(s):  
Lihong Cao ◽  
Donna Wallace ◽  
Lynda Tuttle ◽  
Kirk Martin
Keyword(s):  
Image Quality ◽  
Flip Chip ◽  
Thermal Emission ◽  
Photon Emission ◽  
Fault Isolation ◽  
Isolation Techniques ◽  
High Uniformity ◽  
Localization Analysis ◽  
Mechanical Thinning ◽  
The Impact

Abstract Mechanical thinning of Si die backside was introduced to support fault isolation for flip chip package in this paper. The backside milling system provides two types of thinning with good die planarity and mirror polishing to yield a high image quality for fault isolation techniques such as laser base thermal emission and photon emission techniques. In this paper, two mechanical thinning techniques were applied by using the 3D die curvature thinning and 2D planar thinning on flip chip Si backside. The impact of process parameters on die planarity and fault isolation were also discussed. The experimental results demonstrate the milling system’s high uniformity across the large die size and provide a very good solution for fault isolation techniques.

scholarly journals Simulation of cooling efficiency via miniaturised channels in multilayer LTCC for power electronics

2017 ◽  
Vol 68 (2) ◽  
pp. 132-137 ◽  
Author(s):  
Alena Pietrikova ◽  
Tomas Girasek ◽  
Peter Lukacs ◽  
Tilo Welker ◽  
Jens Müller
Keyword(s):  
Thermal Resistance ◽  
New Technology ◽  
Flow Analysis ◽  
Simulation Software ◽  
Volume Flow ◽  
Cooling Power ◽  
Cooling Channels ◽  
Power Modules ◽  
The Impact ◽  
Ltcc Substrate

Abstract The aim of this paper is detailed investigation of thermal resistance, flow analysis and distribution of coolant as well as thermal distribution inside multilayer LTCC substrates with embedded channels for power electronic devices by simulation software. For this reason four various structures of internal channels in the multilayer LTCC substrates were designed and simulated. The impact of the volume flow, structures of channels, and power loss of chip was simulated, calculated and analyzed by using the simulation software Mentor Graphics FloEFDTM. The structure, size and location of channels have the significant impact on thermal resistance, pressure of coolant as well as the effectivity of cooling power components (chips) that can be placed on the top of LTCC substrate. The main contribution of this paper is thermal analyze, optimization and impact of 4 various cooling channels embedded in LTCC multilayer structure. Paper investigate, the effect of volume flow in cooling channels for achieving the least thermal resistance of LTCC substrate that is loaded by power thermal chips. Paper shows on the impact of the first chips thermal load on the second chip as well as. This possible new technology could ensure in the case of practical realization effective cooling and increasing reliability of high power modules.

A Circular-Disk Dielectric Resonator for Low-Temperature Magnetic Resonance Measurements at Millimeter and Sub-Millimeter Wavelengths

2008 ◽  
Vol 67 (14) ◽  
pp. 1239-1245
Author(s):  
V. N. Derkach ◽  
T. V. Bagmut ◽  
R. V. Golovashchenko ◽  
V. G. Korzh ◽  
S. V. Nedukh ◽  
...  
Keyword(s):  
Magnetic Resonance ◽  
Low Temperature ◽  
Dielectric Resonator ◽  
Circular Disk ◽  
Millimeter Wavelengths

Electron Beam Absorbed Current as a Means of Locating Metal Defectivity on 45nm SOI Technology

2010 ◽  
Author(s):  
K. Dickson ◽  
G. Lange ◽  
K. Erington ◽  
J. Ybarra
Keyword(s):  
Electron Beam ◽  
Flip Chip ◽  
Back Side ◽  
Soi Technology

Abstract This paper describes the use of Electron Beam Absorbed Current (EBAC) mapping performed from the back side of the device as a means of locating metallization defects on flip chip 45nm SOI technology.

VLSI Design for Functional Failure Analysis in the < 90 nm and Flip-Chip Era

2003 ◽  
Author(s):  
Yoav Weizman ◽  
Ezra Baruch
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
Light Emission ◽  
Vlsi Design ◽  
Optical Resolution ◽  
Critical Issue ◽  
Acquisition Time ◽  
Resolution Limit ◽  
Design Rules ◽  
The Impact

Abstract In recent years, two new techniques were introduced for flip chip debug; the Laser Voltage Probing (LVP) technique and Time Resolved Light Emission Microscopy (TRLEM). Both techniques utilize the silicon’s relative transparency to wavelengths longer than the band gap. This inherent wavelength limitation, together with the shrinking dimensions of modern CMOS devices, limit the capabilities of these tools. It is known that the optical resolution limits of the LVP and TRLEM techniques are bounded by the diffraction limit which is ~1um for both tools using standard optics. This limitation was reduced with the addition of immersion lens optics. Nevertheless, even with this improvement, shrinking transistor geometry is leading to increased acquisition time, and the overlapping effect between adjacent nodes remains a critical issue. The resolution limit is an order of magnitude above the device feature densities in the &lt; 90nm era. The scaling down of transistor geometry is leading to the inevitable consequence where more than 50% of the transistors in 90nm process have widths smaller than 0.4um. The acquisition time of such nodes becomes unreasonably long. In order to examine nodes in a dense logic cuicuit, cross talk and convolution effects between neighboring signals also need to be considered. In this paper we will demonstrate the impact that these effects may have on modern design. In order to maintain the debug capability, with the currently available analytical tools for future technologies, conceptual modification of the FA process is required. This process should start on the IC design board where the VLSI designer should be familiar with FA constraints, and thus apply features that will enable enhanced FA capabilities to the circuit in hand during the electrical design or during the physical design stages. The necessity for reliable failure analysis in real-time should dictate that the designer of advanced VLSI blocks incorporates failure analysis constraints among other design rules. The purpose of this research is to supply the scientific basis for the optimal incorporation of design rules for optical probing in the &lt; 90nm gate era. Circuit designers are usually familiar with the nodes in the design which are critical for debug, and the type of measurement (logic or DC level) they require. The designer should enable the measurement of these signals by applying certain circuit and physical constraints. The implementation of these constraints may be done at the cell level, the block level or during the integration. We will discuss the solutions, which should be considered in order to mitigate tool limitations, and also to enable their use for next generation processes.

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