ESD implantations in 0.18-μm salicided CMOS technology for on-chip ESD protection with layout consideration

2002 ◽  
Author(s):  
Ming-Dou Ker ◽  
Che-Hao Chuang
Keyword(s):  
Cmos Technology ◽  
Esd Protection ◽  
On Chip

P-45: On-Chip ESD Protection Design for UXGA/HDTV LCoS in 0.35-μm CMOS Technology

2004 ◽  
Vol 35 (1) ◽  
pp. 404
Author(s):  
Ming-Dou Ker ◽  
Shih-Hung Chen ◽  
Tang-Kui Tseng
Keyword(s):  
Cmos Technology ◽  
Esd Protection ◽  
On Chip

On-Chip ESD Protection Device for High-Speed I/O Applications in CMOS Technology

2017 ◽  
Vol 64 (10) ◽  
pp. 3979-3985 ◽  
Author(s):  
Jie-Ting Chen ◽  
Chun-Yu Lin ◽  
Ming-Dou Ker
Keyword(s):  
High Speed ◽  
Cmos Technology ◽  
Protection Device ◽  
Esd Protection ◽  
On Chip
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