65nm Cu Integration and Interconnect Reliability in Low Stress K=2.75 SiCOH

2006 ◽  
Author(s):  
V. McGahay ◽  
G. Bonilla ◽  
F. Chen ◽  
C. Christiansen ◽  
S. Cohen ◽  
...  
Keyword(s):  
Interconnect Reliability

Interconnect reliability dependence on fast diffusivity paths

2012 ◽  
Vol 52 (8) ◽  
pp. 1532-1538 ◽  
Author(s):  
Hajdin Ceric ◽  
Roberto Lacerda de Orio ◽  
Siegfried Selberherr
Keyword(s):  
Interconnect Reliability

The Microstructural Nature of Electromigration and Mechanical Stress Voids in Integratedcircuit Interconnect

1993 ◽  
Vol 309 ◽  
Author(s):  
Jamie H. Rose ◽  
Terry Spooner
Keyword(s):  
Grain Boundary ◽  
Integrated Circuit ◽  
Boundary Diffusion ◽  
Void Formation ◽  
Parallel Line ◽  
Relative Displacement ◽  
Test Conditions ◽  
Line Array ◽  
Interconnect Reliability ◽  
Diffusion Paths

AbstractIt is well known that stress and electromigration induced voiding is of major concern for integrated circuit interconnect reliability. However, there has been little systematiccharacterization of void morphology and crystallography in ever more technologically important narrow, “near-bamboo” conducting lines. Prior reports indicate thatvoids are typically wedge or slit shaped, with failure often associated with slit voids.Void face habit plane is most often reported to be {111}. Wedge and slit void morphology and crystallography have been studied in comb/serpentine and parallel line array test structures. In virtually all cases, void faces are {111} oriented. In contrast to earlier studies, intragranular wedge stress voids have been observed. All electromigration opens were due to slit voids; these were typically intragranular, in contradiction to current theories of void formation, and likely are mechanical fractures. Under accelerated test conditions, non-grain boundary diffusion paths appear to operate at distances of tens of micrometers. Relative displacement between wedge voids and attached grain boundaries occurs where a wedge face lies on a near common {111} plane for the two grains. It is suggested that slit voids are intragranular under both stress and electromigration conditions and likely associated with local interconnect depassivation. Based solely on appearance and crystallography, no void can uniquely be identified as due to stress alone or electromigration alone.

Reliability Assessment and Failure Analysis of G-Helix, a Free-Standing Compliant Off-Chip Interconnect

2009 ◽  
Vol 6 (1) ◽  
pp. 59-65
Author(s):  
Karan Kacker ◽  
Suresh K. Sitaraman
Keyword(s):  
Failure Analysis ◽  
Dielectric Material ◽  
Organic Substrate ◽  
Wafer Level ◽  
Free Standing ◽  
Fine Pitch ◽  
Cross Section Area ◽  
Interconnect Reliability ◽  
Compliant Interconnect ◽  
Low K

Continued miniaturization in the microelectronics industry calls for chip-to-substrate off-chip interconnects that have 100 μm pitch or less for area-array format. Such fine-pitch interconnects will have a shorter standoff height and a smaller cross-section area, and thus could fail through thermo-mechanical fatigue prematurely. Also, as the industry transitions to porous low-K dielectric/Cu interconnect structures, it is important to ensure that the stresses induced by the off-chip interconnects and the package configuration do not crack or delaminate the low-K dielectric material. Compliant free-standing structures used as off-chip interconnects are a potential solution to address these reliability concerns. In our previous work we have proposed G-Helix interconnects, a lithography-based electroplated compliant off-chip interconnect that can be fabricated at the wafer level. In this paper we develop an assembly process for G-Helix interconnects at a 100 μm pitch, identifying the critical factors that impact the assembly yield of such free-standing compliant interconnect. Reliability data are presented for a 20 mm × 20 mm chip with G-Helix interconnects at a 100 μm pitch assembled on an organic substrate and subjected to accelerated thermal cycling. Subsequent failure analysis of the assembly is performed and limited correlation is shown with failure location predicted by finite elements models.

Development of 3D System-in-Package with TSV Technology

2014 ◽  
Vol 2014 (1) ◽  
pp. 000612-000617 ◽  
Author(s):  
Shota Miki ◽  
Takaharu Yamano ◽  
Sumihiro Ichikawa ◽  
Masaki Sanada ◽  
Masato Tanaka
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Organic Substrate ◽  
Back Side ◽  
Final Thickness ◽  
Chip Technology ◽  
Type Semiconductor ◽  
Interconnect Reliability ◽  
Solder Balls ◽  
Carrier Wafer

In recent years, products such as smart phones, tablets, and wearable devices, are becoming miniaturized and high performance. 3D-type semiconductor structures are advancing as the demand for high-density assembly increases. We studied a fabrication process using a SoC die and a memory die for 3D-SiP (System in Package) with TSV technology. Our fabrication is comprised of two processes. One is called MEOL (Middle End of Line) for exposing and completing the TSV's in the SoC die, and the other is assembling the SoC and memory dice in a 3D stack. The TSV completion in MEOL was achieved by SoC wafer back-side processing. Because its final thickness will be a thin 50μm (typical), the SoC wafer (300 mm diameter) is temporarily attached face-down onto a carrier-wafer. Careful back-side grinding reveals the “blind vias” and fully opens them into TSV's. A passivation layer is then grown on the back of the wafer. With planarization techniques, the via metal is accessed and TSV pads are built by electro-less plating without photolithography. After the carrier-wafer is de-bonded, the thin wafer is sawed into dice. For assembling the 3D die stack, flip-chip technology by thermo-compression bonding was the method chosen. First, the SoC die with copper pillar bumps is assembled to the conventional organic substrate. Next the micro-bumps on the memory die are bonded to the TSV pads of the SoC die. Finally, the finished assembly is encapsulated and solder balls (BGA) are attached. The 3D-SiP has passed both package-level reliability and board-level reliability testing. These results show we achieved fabricating a 3D-SiP with high interconnect reliability.

scholarly journals Enhancing Interconnect Reliability and Performance by Converting Tantalum to 2D Layered Tantalum Sulfide at Low Temperature

2019 ◽  
pp. 1902397 ◽  
Author(s):  
Chun‐Li Lo ◽  
Massimo Catalano ◽  
Ava Khosravi ◽  
Wanying Ge ◽  
Yujin Ji ◽  
...  
Keyword(s):  
Low Temperature ◽  
Tantalum Sulfide ◽  
Interconnect Reliability ◽  
And Performance
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