A high density 0.10 μm CMOS technology using low K dielectric and copper interconnect

Author(s):  
S. Parihar ◽  
M. Angyal ◽  
B. Boeck ◽  
D. Reber ◽  
A. Singhal ◽  
...  
2004 ◽  
Vol 812 ◽  
Author(s):  
Charlie Jun Zhai ◽  
Paul R. Besser ◽  
Frank Feustel

AbstractThe damascene fabrication method and the introduction of low-K dielectrics present a host of reliability challenges to Cu interconnects and fundamentally change the mechanical stress state of Cu lines. In order to capture the effect of individual process steps on the stress evolution in the BEoL (Back End of Line), a process-oriented finite element modeling (FEM) approach was developed. In this model, the complete stress history at any step of BEoL can be simulated as a dual damascene Cu structure is fabricated. The inputs to the model include the temperature profile during each process step and materials constants. The modeling results are verified in two ways: through wafer-curvature measurement during multiple film deposition processes and with X-Ray diffraction to measure the mechanical stress state of the Cu interconnect lines fabricated using 0.13um CMOS technology. The Cu line stress evolution is simulated during the process of multi-step processing for a dual damascene Cu/low-K structure. It is shown that the in-plane stress of Cu lines is nearly independent of subsequent processes, while the out-of-plane stress increases considerably with the subsequent process steps.


2008 ◽  
Vol 1 ◽  
pp. 189-196 ◽  
Author(s):  
Sonanvane Avinash ◽  
Bhavana N. Joshi ◽  
Ashok Madhu Mahajan
Keyword(s):  

Author(s):  
Y.-L. Shen

Systematic finite element analyses are carried out to model the thermomechanical stresses in on-chip copper interconnect systems. Constitutive behavior of encapsulated copper films, determined by experimentally measuring the stress-temperature response during thermal cycling, is used in the model for predicting stresses in copper interconnect/low-k dielectric structures. Various combinations of oxide and polymer-based low-k dielectric schemes are considered. The evolution of stresses and deformation pattern in the dual-damascene copper, barrier layers, and the dielectrics is seen to have direct connections to the structural integrity of contemporary and future-generation devices. In particular, stresses experienced by the thin barrier layers and the mechanically weak low-k dielectrics are critically assessed. A parametric analysis on the influence of low-k material properties is also conducted. Practical implications in reliability issues such as voiding, interface fracture, electromigration and dielectric failure are discussed.


Nanomaterials ◽  
2020 ◽  
Vol 10 (5) ◽  
pp. 966
Author(s):  
Antonio Alessio Leonardi ◽  
Maria José Lo Faro ◽  
Alessia Irrera

Silicon nanowires (Si NWs) are emerging as an innovative building block in several fields, such as microelectronics, energetics, photonics, and sensing. The interest in Si NWs is related to the high surface to volume ratio and the simpler coupling with the industrial flat architecture. In particular, Si NWs emerge as a very promising material to couple the light to silicon. However, with the standard synthesis methods, the realization of quantum-confined Si NWs is very complex and often requires expensive equipment. Metal-Assisted Chemical Etching (MACE) is gaining more and more attention as a novel approach able to guarantee high-quality Si NWs and high density with a cost-effective approach. Our group has recently modified the traditional MACE approach through the use of thin metal films, obtaining a strong control on the optical and structural properties of the Si NWs as a function of the etching process. This method is Complementary Metal-Oxide-Semiconductors (CMOS)-technology compatible, low-cost, and permits us to obtain a high density, and room temperature light-emitting Si NWs due to the quantum confinement effect. A strong control on the Si NWs characteristics may pave the way to a real industrial transfer of this fabrication methodology for both microelectronics and optoelectronics applications.


2001 ◽  
pp. 1520-1523 ◽  
Author(s):  
X. Zhu ◽  
S. Santhanam ◽  
H. Lakdawala ◽  
H. Luo ◽  
G. K. Fedder
Keyword(s):  

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