Electron transport through accumulation layers and its effect on the series resistance of MOS transistors

2002 ◽  
Author(s):  
E.A. Gutierrez-D ◽  
O. Gonzalez-C ◽  
R.S. Murphy-A
Keyword(s):  
Electron Transport ◽  
Series Resistance ◽  
Mos Transistors

scholarly journals Series resistance effects in submicron MOS transistors operated from 300 K down to 4.2 K

1994 ◽  
Vol 04 (C6) ◽  
pp. C6-31-C6-36
Author(s):  
E. A. Gutiérrez-D ◽  
L. Deferm ◽  
G. Declerck
Keyword(s):  
Series Resistance ◽  
Mos Transistors

Influence of series resistance determination on the extracted mobility in MOS transistors with Ge channel

2013 ◽  
Author(s):  
Jakub Jasiński ◽  
Lidia Łukasiak ◽  
Andrzej Jakubowski ◽  
Catarina Casteleiro ◽  
Terry E. Whall ◽  
...  
Keyword(s):  
Series Resistance ◽  
Mos Transistors

Effect of Spacer Scaling on PMOS Transistors

2006 ◽  
Vol 913 ◽  
Author(s):  
Wai Shing Lau ◽  
Chee Wee Eng ◽  
David Vigar ◽  
Lap Chan ◽  
Soh Yun Siah
Keyword(s):  
Linear Relationship ◽  
Series Resistance ◽  
State Of The Art ◽  
Resistance Mechanism ◽  
Channel Length ◽  
Mos Transistors ◽  
Effective Channel

AbstractOur observation is that both the on-current and off-current of state-of-the-art p-channel MOS transistors tend to become larger when the L-shaped spacer becomes smaller due to two different mechanisms: a decrease in the effective channel length Leff (Mechanism A) and a decrease in the series resistance (Mechanism B). In our analysis, we use drain induced barrier lowering (DIBL) as a measure of Leff and we assume that there is a linear relationship between the on-current, the logarithm of the off current and DIBL. Our assumption is supported by our theoretical derivations.

Behavior of contact-silicided TFSOI gate structures

1994 ◽  
Vol 52 ◽  
pp. 860-861
Author(s):  
N. David Theodore ◽  
Juergen Foerstner ◽  
Peter Fejes
Keyword(s):  
Semiconductor Device ◽  
Series Resistance ◽  
Field Effect Transistors ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
Continuous Layer ◽  
Buried Oxide ◽  
Device Structures ◽  
Thin Silicon

As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of thin-film silicon-on-insulator (TFSOI) substrates for device fabrication is being explored in order to increase switching speeds. One version of TFSOI being explored for device fabrication is SIMOX (Silicon-separation by Implanted OXygen).A buried oxide layer is created by highdose oxygen implantation into silicon wafers followed by annealing to cause coalescence of oxide regions into a continuous layer. A thin silicon layer remains above the buried oxide (~220 nm Si after additional thinning). Device structures can now be fabricated upon this thin silicon layer.Current fabrication of metal-oxidesemiconductor field-effect transistors (MOSFETs) requires formation of a polysilicon/oxide gate between source and drain regions. Contact to the source/drain and gate regions is typically made by use of TiSi2 layers followedby Al(Cu) metal lines. TiSi2 has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions

The role of ligands in electron transport in nanocrystal solids

Nanoscale ◽  
2020 ◽  
Vol 12 (45) ◽  
pp. 23028-23035
Author(s):  
Artem R. Khabibullin ◽  
Alexander L. Efros ◽  
Steven C. Erwin
Keyword(s):  
Electron Transport ◽  
Theoretical Modeling

Theoretical modeling of wavefunction overlap in nanocrystal solids elucidates the important role played by ligands in electron transport.

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