An Approach For Drain Current Modeling Including Quantum Mechanical Effects For A DMDG Junctionless Field Effect Nanowire Transistor

This paper presents the effects of quantum confinements on the surface potential, threshold voltage, drain current, transconductance, and drain conductance of a Dual Material Double Gate Junctionless Field Effect Nanowire Transistor (DMDG-JLFENT). The carrier energy quantization on the threshold voltage of a DMDG-JLFENT is modeled, and subsequently, other parameters like drain current were analytically presented. The QME considered here is obtained under the quantum confinement condition for an ultra-thin channel, i.e., below 10 nm of Si thickness. The threshold voltage shift due to QME can be used as a quantum correction term for compact modeling of junctionless transistors. The analytical model proposed for surface potential, threshold voltage, drain current, transconductance, and drain conductance were verified by TCAD 3-D quantum simulation results which makes it suitable for SPICE compact modeling.

A Drain Current and Transconductance Analytical Model for Symmetric Double Gate Junctionless FENT

This paper presents an analytical model of various electrical parameters for an ultra thin symmetric double gate (SDG) junctionless field effect nanowire transistor (JLFENT). The model works for all the regions of operation of the nanowire transistor without using any fitting parameter. The surface potential is derived based on the solutions of Poisson’s and current continuity equations by using appropriate boundary conditions. The Pao–Sah double integral was used to obtain the drain current, transconductance and drain conductance. The results obtained from analytical model are validated by comparing with GENIUS 3D TCAD simulations. The simplicity of the model makes it appropriate to be a SPICE compatible model.

A compact model of transconductance and drain conductance for DMG-GC-DOT cylindrical gate MOSFET

A compact model for dual-material gate graded-channel and dual-oxide<br />thickness with two dielectric constant different cylindrical gate (DMG-GC-<br />DOTTDCD) MOSFET was investigated in terms of transconductance, drain<br />conductance and capacitance. Short channel effects are modeled with simple<br />expressions, and incorporated into the core of the model (at the drain<br />current). The design effectiveness of DMG-GC-DOTTDCD was monitored<br />in comparing with the DMG-GC-DOT transistor, the effect of variations of<br />technology parameters, was presented in terms of gate polarization and drain<br />polarization. The results indicate that the DMG-GC-DOTTDCD devices<br />have characteristics higher than the DMG-GC-DOT MOSFET. To validate<br />the proposed model, we used the results obtained from the simulation of the<br />device with the SILVACO-ATLAS-TCAD software.