Fault Modeling of Combinational and Sequential Circuits at Register Transfer Level

M S Suma

doi:10.5121/vlsic.2011.2406

A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits

21st International Conference on VLSI Design (VLSID 2008) ◽

10.1109/vlsi.2008.56 ◽

2008 ◽

Cited By ~ 2

Author(s):

Sriram Sambamurthy ◽

Jacob A. Abraham ◽

Raghuram S. Tupuri

Keyword(s):

Power Estimation ◽

Register Transfer Level ◽

Sequential Circuits ◽

Top Down ◽

Dynamic Power ◽

Register Transfer

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A test evaluation technique for vlsi circuits using register-transfer level fault modeling

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2003.814958 ◽

2003 ◽

Vol 22 (8) ◽

pp. 1104-1113 ◽

Cited By ~ 14

Author(s):

P.A. Thaker ◽

V.D. Agrawal ◽

M.E. Zaghloul

Keyword(s):

Fault Modeling ◽

Register Transfer Level ◽

Vlsi Circuits ◽

Test Evaluation ◽

Evaluation Technique ◽

Register Transfer

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Register-transfer level fault modeling and test evaluation techniques for VLSI circuits

Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159) ◽

10.1109/test.2000.894305 ◽

2002 ◽

Cited By ~ 15

Author(s):

P.A. Thaker ◽

V.D. Agrawal ◽

M.E. Zaghloul

Keyword(s):

Fault Modeling ◽

Register Transfer Level ◽

Vlsi Circuits ◽

Test Evaluation ◽

Register Transfer ◽

Evaluation Techniques

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Standard for Verilog register transfer level synthesis

10.3403/30128339u ◽

2015 ◽

Keyword(s):

Register Transfer Level ◽

Register Transfer

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Incorporating the controller effects during register transfer level synthesis

Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC ◽

10.1109/edtc.1994.326916 ◽

2002 ◽

Cited By ~ 4

Author(s):

C. Ramachandran ◽

F.J. Kurdahi

Keyword(s):

Register Transfer Level ◽

Register Transfer

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A non-scan DFT method at register-transfer level to achieve complete fault efficiency

Proceedings of the 2000 conference on Asia South Pacific design automation - ASP-DAC '00 ◽

10.1145/368434.368825 ◽

2000 ◽

Cited By ~ 12

Author(s):

Satoshi Ohtake ◽

Hiroki Wada ◽

Toshimitsu Masuzawa ◽

Hideo Fujiwara

Keyword(s):

Dft Method ◽

Register Transfer Level ◽

Register Transfer

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Test pattern generators for distributed and embedded built-in self-test at register transfer level

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design ◽

10.1109/isqed.2001.915236 ◽

2002 ◽

Author(s):

V. Vorisek

Keyword(s):

Test Pattern ◽

Register Transfer Level ◽

Register Transfer ◽

Self Test ◽

Built In Self Test ◽

Pattern Generators

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A Formal Approach to Confidentiality Verification in SoCs at the Register Transfer Level

10.1109/dac18074.2021.9586248 ◽

2021 ◽

Author(s):

Johannes Muller ◽

Mohammad Rahmani Fadiheh ◽

Anna Lena Duque Anton ◽

Thomas Eisenbarth ◽

Dominik Stoffel ◽

...

Keyword(s):

Register Transfer Level ◽

Formal Approach ◽

Register Transfer

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A Register Transfer Level Approach for Intermittent Semi-Concurrent Error Detection

2010 2nd International Conference on E-business and Information System Security ◽

10.1109/ebiss.2010.5473579 ◽

2010 ◽

Author(s):

Donghu Yang ◽

Jianhui Jiang ◽

Jie Yin ◽

Jipeng Huang

Keyword(s):

Error Detection ◽

Register Transfer Level ◽

Concurrent Error Detection ◽

Register Transfer

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Efficient Digital System Design Methodology with SystemC Register Transfer Level Modeling

IEEE SoutheastCon, 2004. Proceedings. ◽

10.1109/secon.2004.1287966 ◽

2004 ◽

Author(s):

M.C. Zabawa ◽

S.V. Wunnava

Keyword(s):

System Design ◽

Design Methodology ◽

Register Transfer Level ◽

Digital System ◽

Register Transfer ◽

Digital System Design

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