Test Chip for Characterization of Mechanical Stress Caused by Packaging Processes

2006 ◽  
Author(s):  
Soeren Hirsch ◽  
Marc-peter Schmidt ◽  
Bertram Schmidt
Keyword(s):  
Mechanical Stress ◽  
Test Chip

Experimental Characterization of the Vertical and Lateral Heat Transfer in 3D-SIC Packages

2015 ◽  
Author(s):  
Herman Oprins ◽  
Vladimir Cherman ◽  
Geert Van der Plas ◽  
Joeri De Vos ◽  
Eric Beyne
Keyword(s):  
Power Distribution ◽  
Hot Spot ◽  
Lateral Spreading ◽  
Experimental Characterization ◽  
Test Chip ◽  
Conductivity Increase ◽  
Thermal Conductivity Increase ◽  
Equivalent Properties ◽  
Lateral Heat

In this paper, we present the experimental characterization of 3D packages using a dedicated stackable test chip. An advanced CMOS test chip with programmable power distribution has been designed, fabricated, stacked and packaged in molded and bare die 3D packages. The packages have been experimentally characterized in test sockets with and without cooling, and soldered to the PCB. Using uniform and localized hot spot power distribution, the thermal self-heating and thermal coupling resistance and the lateral spreading in the 3D packages have been studied. Furthermore, the measurements have been used to characterize the thermal properties of the epoxy mold compound and the die-die interface and to calibrate a thermal model for the calculation of equivalent properties of underfilled μbump arrays. This model has been applied to study the trade-off between the stand-off height reduction and the underfill thermal conductivity increase in order to reduce the inter die thermal resistance.

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