Local transformation techniques for multi-level logic circuits utilizing circuit symmetries for power reduction

1998 ◽  
Author(s):  
Ki-Seok Chung ◽  
C. L. Liu
Keyword(s):  
Logic Circuits ◽  
Power Reduction ◽  
Local Transformation ◽  
Transformation Techniques ◽  
Multi Level

Power optimization of multi-level logic circuits utilizing circuit symmetries

2000 ◽  
Vol 87 (7) ◽  
pp. 853-864
Author(s):  
Ki-Seok Chung ◽  
Taewhan Kim ◽  
C. L. Liu
Keyword(s):  
Power Optimization ◽  
Logic Circuits ◽  
Multi Level

Effective Circuit Design Methodologies for Standby Leakage Power Reduction

2020 ◽  
Vol 12 (2) ◽  
pp. 168-172
Author(s):  
Manish Kumar ◽  
Md. Anwar Hussain ◽  
Sajal K. Paul
Keyword(s):  
Circuit Design ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Logic Circuits ◽  
Power Reduction ◽  
Leakage Power ◽  
Model Parameters ◽  
Mos Transistor ◽  
Design Methodologies ◽  
Transistor Model

This paper presents circuit level design methodologies for significantly reducing the standby leakage power. Layout of different CMOS logic circuits such as a 2-input XOR, a 2-input XNOR, and a 4-input XNOR are designed and simulated by using BSIM4 MOS transistor model parameters. Layout simulations are done at a supply voltage of 0.4 V in 45 nm CMOS technology. Logic circuits designed by using the proposed circuit design methodologies proved to be effective in minimizing the standby leakage power. All layout design and simulation of the circuits are carried out by using Microwind EDA software (version 3.1).

Integration Challenges of Inorganic Low-K (K≤2.5) Materials with CU for Sub-0.25μm Multilevel Interconnects

1999 ◽  
Vol 565 ◽  
Author(s):  
K. C. Yu ◽  
J. Defilippi ◽  
R. Tiwari ◽  
T. Sparks ◽  
D. Smith ◽  
...  
Keyword(s):  
Isothermal Annealing ◽  
Process Development ◽  
Cmos Technology ◽  
Power Reduction ◽  
Oxide Materials ◽  
Power Devices ◽  
Parametric Data ◽  
Porous Oxide ◽  
Multi Level ◽  
Low K

AbstractThe recent introduction of dual inlaid Cu and oxide based interconnects within sub-0.25μm CMOS technology has delivered higher performance and lower power devices. Further speed improvements and power reduction may be achieved by reducing the interconnect parasitic capacitance through integration of low-k interlevel dielectric (ILD) materials with Cu. This paper demonstrates successful multi-level dual inlaid Cu/low-k interconnects with ILD permittivities ranging from 2.0 to 2.5. Integration challenges specific to inorganic low-k and Cu based structures are discussed. Through advanced CMP process development, multi-level integration of porous oxide materials with moduli less than 0.5 GPa is demonstrated. Parametric data and isothermal annealing of these Cu/ low-k structures show results with yield comparable to Cu/oxide based interconnects.

Multi-Level Optimization for Large Fan-In Optical Logic Circuits Using Integrated Nanophotonics

2018 ◽  
Author(s):  
Takumi Egawa ◽  
Tohru Ishihara ◽  
Hidetoshi Onodera ◽  
Akihiko Shinya ◽  
Shota Kita ◽  
...  
Keyword(s):  
Logic Circuits ◽  
Optical Logic ◽  
Multi Level
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