Copper flip chip bump interconnect technology for microwave subsystems including RF characterization

2002 ◽  
Author(s):  
A. Wong ◽  
D. Linton
Keyword(s):  
Flip Chip ◽  
Interconnect Technology

A Sample Preparation on Decapsulation Methodology for Effective Failure Analysis on Thin Small Leadless (TSLP) Flip Chip Package with Copper Pillar (CuP) Bump Interconnect Technology

2014 ◽  
Author(s):  
Gwee Hoon Yen ◽  
Ng Kiong Kay
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Flip Chip ◽  
Fault Localization ◽  
Cost Effective ◽  
Fault Isolation ◽  
Voltage Contrast ◽  
Interconnect Technology

Abstract Today, failure analysis involving flip chip [1] with copper pillar bump packaging technologies would be the major challenges faced by analysts. Most often, handling on the chips after destructive chemical decapsulation is extremely critical as there are several failure analysis steps to be continued such as chip level fault localization, chip micro probing for fault isolation, parallel lapping [2, 3, 4] and passive voltage contrast. Therefore, quality of sample preparation is critical. This paper discussed and demonstrated a quick, reliable and cost effective methodology to decapsulate the thin small leadless (TSLP) flip chip package with copper pillar (CuP) bump interconnect technology.

New Stacked Die Interconnect Technology for High-Performance and Low-Cost FPGA

2015 ◽  
Vol 12 (3) ◽  
pp. 111-117
Author(s):  
Woon-Seong Kwon ◽  
Suresh Ramalingam ◽  
Xin Wu ◽  
Liam Madden ◽  
C. Y. Huang ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Process Integration ◽  
Cost Effective ◽  
Design Rule ◽  
Innovative Technology ◽  
Wind Condition ◽  
Wafer Level ◽  
Effective Manner ◽  
Interconnect Technology

This article introduces the first comprehensive demonstration of new innovative technology comprising multiple key technologies for highly cost-effective and high-performance Xilinx field programmable gate array (FPGA), which is so-called stack silicon-less interconnect technology (SLIT) that provides the equivalent high-bandwidth connectivity and routing design-rule as stack silicon interconnect (SSI) technology at a cost-effective manner. We have successfully demonstrated the overall process integration and functions of our new SLIT-employed package using Virtex®-7 2000T FPGA product with chip-to-wafer stacking, wafer-level flux cleaning, microbump underfilling, mold encapsulation, and backside silicon removal. Of all technology elements, both full silicon removal process with faster etching and no dielectric layer damage and wafer warpage management after full silicon etching are most crucial elements to realize the SLIT technology. To manage the wafer warpage after full Si removal, a couple of knobs are identified and used such as top reinforcement layer, microbump underfill properties tuning, die thickness, die-to-die space, and total thickness adjustments. It is also discussed in the article how the wafer warpage behaves and how the wafer warpage is managed. New SLIT module shows excellent warpage characteristics of only −30 μm ∼ −40 μm at room temperature (25°C) for 25 mm × 31 mm in size and +20 μm ∼ +25 μm at reflow temperature (250°C). Thermal simulation results shows that thermal resistance of new SLIT package is almost comparable to that of standard 2000T flip-chip ball grid array (FC-BGA) package using through silicon via interposer with standard heat sink configuration and air wind condition. The reliability assessment is now under the study.

40 μm Copper–Silver Composite Flip-Chip Interconnect Technology Using Solid-State Bonding

2012 ◽  
Vol 134 (2) ◽  
Author(s):  
Chu-Hsuan Sha ◽  
Wen P. Lin ◽  
Chin C. Lee
Keyword(s):  
Solid State ◽  
Flip Chip ◽  
Thermal Expansion Mismatch ◽  
Conduction Electrons ◽  
Solid State Bonding ◽  
Cu Substrates ◽  
Atomic Distance ◽  
Free Solder ◽  
Interconnect Technology ◽  
Silver Composite

Copper–silver (Cu–Ag) composite flip-chip interconnect between silicon (Si) chips and Cu substrates is demonstrated. Array of Cu–Ag columns, each 28 μm in height and 40 μm in diameter, is electroplated on 2-in. Si wafers coated with chromium (Cr)/gold (Au) dual layer. The Si wafers are diced into 6 mm × 6 mm chips, each containing 50 × 50 Cu–Ag columns. The Si chip with Cu–Ag columns is bonded to Cu substrates at 260 °C in 80 mTorr vacuum. A bonding force of only 1.8 kg is applied, corresponding to 0.71 g per Cu–Ag column. During bonding, Ag atoms in Cu–Ag columns deform and their surfaces conform to and mate with the surface of Cu substrate. Solid-state bonding incurs when Ag atoms in Cu–Ag columns and Cu atoms in Cu substrates are brought within atomic distance so that they share conduction electrons. The Cu–Ag columns are indeed bonded to the Cu. No molten phase is involved in the bonding. The joint consists of 60% Cu section and 40% Ag section. The ductile Ag is able to accommodate the thermal expansion mismatch between Si and Cu. The Cu–Ag joints do not contain any intermetallic compound (IMC). This interconnect technology avoids all reliability issues associated with IMC growth in conventional soldering processes. Compared to tin-based lead-free solder joints, Cu–Ag composite joints have superior electrical and thermal properties.

Semiconductor-on-Polymer Wafer Level Chip Scale Packaging

2019 ◽  
Vol 2019 (DPC) ◽  
pp. 001232-001256
Author(s):  
Doug Hackler
Keyword(s):  
Flexible Electronics ◽  
Flip Chip ◽  
Electronic System ◽  
New Physics ◽  
Semiconductor Materials ◽  
Wafer Level ◽  
Test Procedures ◽  
Initial Development ◽  
Thin Semiconductor ◽  
Interconnect Technology

Cell phone boards are getting thinner. Labels and tags are getting smarter. Electronics is starting to bend. Consumers think thin is cool. Scaling thickness has and continues to be a key metric in packaging evolution. Chip Scale Packaging (CSP) defines the logical end of package scaling as package area and IC size converge. CSP, as well as the use of bare die, in Direct Chip Attach (DCA) integration pushes the limit of interconnect technology. CSP and implementation of direct interconnect attachment leads to the smallest packages possible. Technology and reliability advances in ultra-thin Semiconductor-on-Polymer (SoP) CSP and direct interconnect assembly is enabling flexible hybrid electronics and sensors today. SoP extends CSP package size reduction to less than 1.0X the die size. Semiconductor-on-Polymer (SoP) CSP results in ultra-thin semiconductor materials that are less than the thickness possible with bare die. SoP was initially introduced to the Flexible Electronics market; the technology has gained interest for conventional low profile, low-mid I/O, DCA type applications. Advanced SoP CSP is an ultra-thin packaging technology that is capable of complete die encapsulation using wafer level processing. Ultra-thin SoP CSP is new package technology. It is applied to fully characterized commercial devices, uses well know semiconductor materials and is generally “qualified by similarity” (QBS). Qualification for flexible applications supplement QBS with test procedures derived from established standards. The initial development of test methods and procedures was done with AFRL support in 2017. Initial reliability for the new flexibility tests will be presented. SoP CSP is undergoing further characterization for conventional applications. This includes testing that is typical of non-hermetic fully encapsulated parts. Flip-chip is the preferred method for assembly of SoP CSP. The ultra-thin package technology feature is fully utilized using Direct Interconnect (DI). Direct interconnect (DI) is defined as the die pad interconnect technology where the pad is connected directly to a board pad of equivalent size and spacing. Direct interconnect is common for low pad count devices such as RFID, NFC and other DCA applications. Direct interconnect is not typically considered for higher pin count devices…until now. This presentation shares the development of SoP CSP DI assembly that has progressed from 24 pin attachment to System-on-Chip assembly of DI pitch at <100um. The presentation also shows the technology roadmap for SoP CSP evolution. A case study of a SoP CSP application will be included with data from a fully assembled ultra-thin electronic system based on a SoP CSP SOC with total thickness less than 30um. The system includes on-board ultra-thin fully flexible sensors. A call to action will be made to embrace ultra-thin electronics. System Designers and IC Engineers will be encouraged to: BUILD! Create the vision for ultra-thin possibilities. Put electronics into places and things never before possible with, prototypes, testing, reporting, and introducing new thin concepts. Reliability Leaders will be encouraged to: TEST! Update test procedures and standards to include physical deformations and then report and challenge the industry to improve. Universities will be called to: CREATE! Generate new physics/models associated with deformations, develop interconnect innovations and advance new materials. In general, the presentation makes the case that hardware matters – Let's build some new technology.

New Flip-Chip Interconnect Technology for High Performance and High Reliability Applications

2013 ◽  
Vol 52 (1) ◽  
pp. 709-715 ◽  
Author(s):  
E. Yamaguchi ◽  
M. Tsuji ◽  
N. Shimoishizaka ◽  
T. Nakano ◽  
K. Hirata
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
High Reliability ◽  
Interconnect Technology

40 μm Silver Flip-Chip Interconnect Technology With Solid-State Bonding

2011 ◽  
Vol 133 (3) ◽  
Author(s):  
Chu-Hsuan Sha ◽  
Chin C. Lee
Keyword(s):  
Flip Chip ◽  
Bonding Process ◽  
Thermal Expansion Mismatch ◽  
Pure Silver ◽  
Bonding Pressure ◽  
Cu Substrate ◽  
Solid State Bonding ◽  
Cu Substrates ◽  
Lead Free Solders ◽  
Interconnect Technology

Formation of pure silver (Ag) flip-chip interconnect of silicon (Si) chips on copper (Cu) substrates is reported. Arrays of Ag columns, each 36 μm in height and 40 μm in diameter, are fabricated on 2-in. Si wafers which are first coated with chromium (Cr)/gold (Au) dual layers. The Si wafers are diced into 6 mm × 6 mm chips, each having 50 × 50 Ag columns. The Si chip with Ag columns is directly bonded to Cu substrate at 260 °C in 80 mTorr vacuum to inhibit oxidation. The static bonding pressure is as low as 680 psi (4.69 MPa), corresponding to a load of 0.021 oz (0.60 g) per column. During bonding, the Ag columns deform and conform to the Cu substrate. They are well bonded to the Cu. No molten phase is involved in the bonding process. The joints consist of pure Ag only. The ductile Ag joints are able to accommodate the thermal expansion mismatch between Si and Cu. It is well known that in nearly all soldering processes used in electronic industries, intermetallic compound (IMC) formation is essential to make a solder joint. In the pure Ag interconnect, no IMCs exist. Thus, reliability issues associated with IMCs are eliminated. Compared to tin-based lead-free solders, pure Ag joints have superior electrical and thermal properties.

Correlation Between the Mechanical Strength and Curing Condition of No-Flow Flip Chip Assemblies

2002 ◽  
Vol 124 (4) ◽  
pp. 397-402 ◽  
Author(s):  
C. W. Tang ◽  
Y. C. Chan ◽  
K. C. Hung ◽  
P. L. Tu
Keyword(s):  
Mechanical Strength ◽  
High Performance ◽  
Flip Chip ◽  
Low Cost ◽  
Under Bump Metallization ◽  
Assembly Technique ◽  
Curing Condition ◽  
Flip Chip Assembly ◽  
Relationship Of ◽  
Interconnect Technology

Flip chip is the emerging interconnect technology for the next generation of high performance electronics. To eliminate the process bottlenecks associated with flip chip assembly, a new assembly technique based around “No-flow” underfill formulations has been proposed. In this paper, we have studied the correlation between the mechanical strength and the curing condition of no-flow flip chip assemblies using six different reflow profiles. It is found that both Ni3Sn4 and Cu6Sn5 intermetallics (IMCs) are formed at the solder/substrate pad and UBM (Under Bump Metallization)/solder interfaces respectively. The thickness of both IMCs increase with the increasing heating factor. The characteristics of the mechanical strength of these IMCs have been demonstrated. A correlation between the mechanical strength and the interfacial metallurgical reaction has been discussed. Also, the fastest possible reflow profile for both the cure of the underfill and maximizing the shear strength is identified. Based on the observed relationship of the mechanical strength and underfill curing of no-flow flip chip assemblies with Qn, the reflow profile should be controlled with caution in order to optimize both the mechanical strength and time for underfill cure. Only a clearer understanding of these correlation can allow manufacturers to develop a optimal, high reliable, low cost, high throughput no-flow flip chip assembly process.

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