New Stacked Die Interconnect Technology for High-Performance and Low-Cost FPGA

2015 ◽  
Vol 12 (3) ◽  
pp. 111-117
Author(s):  
Woon-Seong Kwon ◽  
Suresh Ramalingam ◽  
Xin Wu ◽  
Liam Madden ◽  
C. Y. Huang ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Process Integration ◽  
Cost Effective ◽  
Design Rule ◽  
Innovative Technology ◽  
Wind Condition ◽  
Wafer Level ◽  
Effective Manner ◽  
Interconnect Technology

This article introduces the first comprehensive demonstration of new innovative technology comprising multiple key technologies for highly cost-effective and high-performance Xilinx field programmable gate array (FPGA), which is so-called stack silicon-less interconnect technology (SLIT) that provides the equivalent high-bandwidth connectivity and routing design-rule as stack silicon interconnect (SSI) technology at a cost-effective manner. We have successfully demonstrated the overall process integration and functions of our new SLIT-employed package using Virtex®-7 2000T FPGA product with chip-to-wafer stacking, wafer-level flux cleaning, microbump underfilling, mold encapsulation, and backside silicon removal. Of all technology elements, both full silicon removal process with faster etching and no dielectric layer damage and wafer warpage management after full silicon etching are most crucial elements to realize the SLIT technology. To manage the wafer warpage after full Si removal, a couple of knobs are identified and used such as top reinforcement layer, microbump underfill properties tuning, die thickness, die-to-die space, and total thickness adjustments. It is also discussed in the article how the wafer warpage behaves and how the wafer warpage is managed. New SLIT module shows excellent warpage characteristics of only −30 μm ∼ −40 μm at room temperature (25°C) for 25 mm × 31 mm in size and +20 μm ∼ +25 μm at reflow temperature (250°C). Thermal simulation results shows that thermal resistance of new SLIT package is almost comparable to that of standard 2000T flip-chip ball grid array (FC-BGA) package using through silicon via interposer with standard heat sink configuration and air wind condition. The reliability assessment is now under the study.

Cost Effective and High Performance 28nm FPGA with New Disruptive Silicon-Less Interconnect Technology (SLIT)

2014 ◽  
Vol 2014 (1) ◽  
pp. 000599-000605 ◽  
Author(s):  
Woon-Seong Kwon ◽  
Suresh Ramalingam ◽  
Xin Wu ◽  
Liam Madden ◽  
C. Y. Huang ◽  
...  
Keyword(s):  
High Performance ◽  
Process Integration ◽  
Cost Effective ◽  
Disruptive Innovation ◽  
Design Rule ◽  
Wind Condition ◽  
Silicon Etching ◽  
Wafer Level ◽  
Effective Manner ◽  
Interconnect Technology

This paper introduces the first comprehensive demonstration of new disruptive innovation technology comprising multiple Xilinx patent-pending innovations for highly cost effective and high performance Xilinx FPGA, which is so called stack silicon-less interconnect technology (SLIT) that provides the equivalent high-bandwidth connectivity and routing design-rule as stack silicon interconnect (SSI) technology at a cost-effective manner. We have successfully demonstrated the overall process integration and functions of our new SLIT-employed package using Virtex® -7 2000T FPGA product. Chip-to-Wafer stacking, wafer level flux cleaning, micro-bump underfilling, mold encapsulation are newly developed. Of all technology elements, both full silicon etching with high etch selectivity to dielectric/fast etch rate and wafer warpage management after full silicon etching are most crucial elements to realize the SLIT technology. In order to manage the wafer warpage after full Si removal, a couple of knobs are identified and employed such as top reinforcement layer, micro-bump underfill properties tuning, die thickness/die-to-die space/total thickness adjustments. It's also discussed in the paper how the wafer warpage behaves and how the wafer warpge is managed. New SLIT module shows excellent warpage characteristics of only −30 μm ~ −40 μm at room temperature for 25 mm × 31 mm in size and +20 μm ~ +25 μm at reflow temperature. Thermal simulation results shows that thermal resistance of new SLIT package is almost comparable to that of standard 2000T FCBGA package using TSV interposer with standard heat sink configuration and air wind condition. The reliability assessment is now under the study.

A Sample Preparation on Decapsulation Methodology for Effective Failure Analysis on Thin Small Leadless (TSLP) Flip Chip Package with Copper Pillar (CuP) Bump Interconnect Technology

2014 ◽  
Author(s):  
Gwee Hoon Yen ◽  
Ng Kiong Kay
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Flip Chip ◽  
Fault Localization ◽  
Cost Effective ◽  
Fault Isolation ◽  
Voltage Contrast ◽  
Interconnect Technology

Abstract Today, failure analysis involving flip chip [1] with copper pillar bump packaging technologies would be the major challenges faced by analysts. Most often, handling on the chips after destructive chemical decapsulation is extremely critical as there are several failure analysis steps to be continued such as chip level fault localization, chip micro probing for fault isolation, parallel lapping [2, 3, 4] and passive voltage contrast. Therefore, quality of sample preparation is critical. This paper discussed and demonstrated a quick, reliable and cost effective methodology to decapsulate the thin small leadless (TSLP) flip chip package with copper pillar (CuP) bump interconnect technology.

Journey Toward Process Convergence in TSV Technology

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 001282-001321
Author(s):  
Sesh Ramaswami ◽  
John Dukovic
Keyword(s):  
Process Integration ◽  
Semiconductor Industry ◽  
Rapid Development ◽  
Chemical Mechanical Planarization ◽  
Cost Effective ◽  
Superior Performance ◽  
Wafer Level ◽  
Unit Process ◽  
Integration Schemes ◽  
Process Convergence

Continuous demand for more advanced electronic devices with higher functionality and superior performance in smaller packages is driving the semiconductor industry to develop new and more advanced 3D wafer-level interconnect technologies involving TSVs (through-silicon vias). The TSVs are created either on full-thickness wafer from the wafer front-side ¡V as part of wafer-fab processing during Middle-Of-Line (¡§via middle¡¨) or Back-End-Of-Line (¡§via last BEOL¡¨) ¡V or from the wafer backside after wafer thinning (¡§via last backside¡¨). Independent of the specific approach, the main steps include via etching, lining with insulator, copper barrier/seed deposition, via fill, and chemical mechanical planarization (CMP). Over the past year, the industry has been converging toward some primary unit processes and integration schemes for creating the TSVs. A common cost-of-ownership framework has also begun to emerge. Active collaboration underway among equipment suppliers, materials providers and end users is bringing about rapid development and validation of cost-effective TSV technology in end products. This presentation will address unit-process and integration challenges of TSV fabrication in the context of 20x100ƒÝm and 5x50ƒÝm baseline process flows at Applied Materials. Highlights of wafer-backside process integration involving wafers bonded to silicon or glass carriers will also be discussed.

Cost Comparison of Fan-out Wafer Level Packaging and Flip Chip Packaging

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-37 ◽  
Author(s):  
Amy Lujan
Keyword(s):  
Flip Chip ◽  
Cost Effective ◽  
Cost Comparison ◽  
Cost Modeling ◽  
Wafer Level ◽  
Design Features ◽  
Wafer Level Packaging ◽  
Flip Chip Packaging ◽  
The Right ◽  
The Cost

In recent years, there has been increased focus on fan-out wafer level packaging with the growing inclusion of a variety of fan-out wafer level packages in mobile products. While fan-out wafer level packaging may be the right solution for many designs, it is not always the lowest cost solution. The right packaging choice is the packaging technology that meets design requirements at the lowest cost. Flip chip packaging, a more mature technology, continues to be an alternative to fan-out wafer level packaging. It is important for many in the electronic packaging industry to be able to determine whether flip chip or fan-out wafer level packaging is the most cost-effective option. This paper will compare the cost of flip chip and fan-out wafer level packaging across a variety of designs. Additionally, the process flows for each technology will be introduced and the cost drivers highlighted. A variety of package sizes, die sizes, and design features will be covered by the cost comparison. Yield is a key component of cost and will also be considered in the analysis. Activity based cost modeling will be used for this analysis. With this type of cost modeling, a process flow is divided into a series of activities, and the total cost of each activity is accumulated. The cost of each activity is determined by analyzing the following attributes: time required, labor required, material required (consumable and permanent), capital required, and yield loss. The goal of this cost comparison is to determine which design features drive a design to be packaged more cost-effectively as a flip chip package, and which design features result in a lower cost fan-out wafer level package.

Wafer Level Assembly Technique Development for Fine Pitch Flip Chip 3D Die-to-Wafer Integration

2010 ◽  
Vol 2010 (1) ◽  
pp. 000548-000553
Author(s):  
Zhaozhi Li ◽  
Brian J. Lewis ◽  
Paul N. Houston ◽  
Daniel F. Baldwin ◽  
Eugene A. Stout ◽  
...  
Keyword(s):  
Flip Chip ◽  
Low Cost ◽  
Three Dimensional ◽  
Cost Effective ◽  
Market Demand ◽  
Wafer Level ◽  
Packaging Technology ◽  
Fine Pitch ◽  
3D Packaging ◽  
Assembly Technique

Three Dimensional (3D) Packaging has become an industry obsession as the market demand continues to grow toward higher packaging densities and smaller form factor. In the meanwhile, the 3D die-to-wafer (D2W) packaging structure is gaining popularity due to its high manufacturing throughput and low cost per package. In this paper, the development of the assembly process for a 3D die-to-wafer packaging technology, that leverages the wafer level assembly technique and flip chip process, is introduced. Research efforts were focused on the high-density flip chip wafer level assembly techniques, as well as the challenges, innovations and solutions associated with this type of 3D packaging technology. Processing challenges and innovations addressed include flip chip fluxing methods for very fine-pitch and small bump sizes; wafer level flip chip assembly program creation and yield improvements; and set up of the Pb-free reflow profile for the assembled wafer. 100% yield was achieved on the test vehicle wafer that has totally 1,876 flip chip dies assembled on it. This work has demonstrated that the flip chip 3D die-to-wafer packaging architecture can be processed with robust yield and high manufacturing throughput, and thus to be a cost effective, rapid time to market alternative to emerging 3D wafer level integration methodologies.

Influence of Socio-Economy in the Next Generation of Thermal Management Solutions for Electronics Consumer Products

2008 ◽  
Author(s):  
Gamal Refai-Ahmed
Keyword(s):  
High Performance ◽  
Heat Dissipation ◽  
Raw Materials ◽  
Cost Effective ◽  
Electronics Packaging ◽  
Consumer Products ◽  
Innovative Technology ◽  
Target Market ◽  
The World ◽  
The Impact

The past few decades have seen a number of countries around the world emerge as a growing market for high performance computers. This present study examines, in more detail, how socio-economic influences are shaping the demand function and how some computing landscapes are changing as a consequence. This study is addressing one of the key initiatives to enable 50 percent of the world’s population with access to the World Wide Web. Furthermore, this investigation is addressing the challenges for electronics packaging Engineers and Researchers. Therefore, the rational of the developed technology based on the understanding target market and usages will be given. The impact of addressing the heat dissipation and managing the use of the raw materials of the intended products are discussed. In addition, how the electronics packaging engineers can focus on developing affordable innovative technology. Finally, the impact of all of the above is examined in developing the cost effective solution from a global point of view.

A Lithography-Based Compliant Chip-to-Substrate Wafer-Level Interconnect

2002 ◽  
Author(s):  
Qi Zhu ◽  
Lunyu Ma ◽  
Suresh K. Sitaraman
Keyword(s):  
High Performance ◽  
Coefficient Of Thermal Expansion ◽  
Low Cost ◽  
Optimization Technique ◽  
Cost Effective ◽  
Organic Substrate ◽  
Electrical Performance ◽  
Wafer Level ◽  
Good Reliability ◽  
Mechanical Compliance

As the rapid advances in IC design and fabrication continue to challenge and push the electronic packaging technology, in terms of fine pitch, high performance, low cost, and good reliability, compliant interconnects show great advantages for next-generation packaging. β-fly is designed as a compliant chip-to-substrate interconnect for performing wafer-level probing and for packaging without underfill. β-fly has good compliance in all directions to compensate the coefficient of thermal expansion (CTE) mismatch between the silicon die and an organic substrate. The fabrication of β-fly is similar to standard IC fabrication, and wafer-level packaging makes it cost effective. In this work, self-weight effect and stress distribution under planar displacement loading of β-fly is studied. The effect of geometry parameters on mechanical and electrical performance of β-fly is also studied. β-fly with thinner and narrower arcuate beams with larger radius and taller post is found to have better mechanical compliance. In addition to mechanical compliance, electrical characteristics of β-fly have also been studied in this work. However, it is found that structures with excellent mechanical compliance cannot have good electrical performance. Therefore, a trade off is needed for the design of β-fly. Response surface methodology and an optimization technique have been used to select the optimal β-fly structure parameters.

Semiconductor-on-Polymer Wafer Level Chip Scale Packaging

2019 ◽  
Vol 2019 (DPC) ◽  
pp. 001232-001256
Author(s):  
Doug Hackler
Keyword(s):  
Flexible Electronics ◽  
Flip Chip ◽  
Electronic System ◽  
New Physics ◽  
Semiconductor Materials ◽  
Wafer Level ◽  
Test Procedures ◽  
Initial Development ◽  
Thin Semiconductor ◽  
Interconnect Technology

Cell phone boards are getting thinner. Labels and tags are getting smarter. Electronics is starting to bend. Consumers think thin is cool. Scaling thickness has and continues to be a key metric in packaging evolution. Chip Scale Packaging (CSP) defines the logical end of package scaling as package area and IC size converge. CSP, as well as the use of bare die, in Direct Chip Attach (DCA) integration pushes the limit of interconnect technology. CSP and implementation of direct interconnect attachment leads to the smallest packages possible. Technology and reliability advances in ultra-thin Semiconductor-on-Polymer (SoP) CSP and direct interconnect assembly is enabling flexible hybrid electronics and sensors today. SoP extends CSP package size reduction to less than 1.0X the die size. Semiconductor-on-Polymer (SoP) CSP results in ultra-thin semiconductor materials that are less than the thickness possible with bare die. SoP was initially introduced to the Flexible Electronics market; the technology has gained interest for conventional low profile, low-mid I/O, DCA type applications. Advanced SoP CSP is an ultra-thin packaging technology that is capable of complete die encapsulation using wafer level processing. Ultra-thin SoP CSP is new package technology. It is applied to fully characterized commercial devices, uses well know semiconductor materials and is generally “qualified by similarity” (QBS). Qualification for flexible applications supplement QBS with test procedures derived from established standards. The initial development of test methods and procedures was done with AFRL support in 2017. Initial reliability for the new flexibility tests will be presented. SoP CSP is undergoing further characterization for conventional applications. This includes testing that is typical of non-hermetic fully encapsulated parts. Flip-chip is the preferred method for assembly of SoP CSP. The ultra-thin package technology feature is fully utilized using Direct Interconnect (DI). Direct interconnect (DI) is defined as the die pad interconnect technology where the pad is connected directly to a board pad of equivalent size and spacing. Direct interconnect is common for low pad count devices such as RFID, NFC and other DCA applications. Direct interconnect is not typically considered for higher pin count devices…until now. This presentation shares the development of SoP CSP DI assembly that has progressed from 24 pin attachment to System-on-Chip assembly of DI pitch at <100um. The presentation also shows the technology roadmap for SoP CSP evolution. A case study of a SoP CSP application will be included with data from a fully assembled ultra-thin electronic system based on a SoP CSP SOC with total thickness less than 30um. The system includes on-board ultra-thin fully flexible sensors. A call to action will be made to embrace ultra-thin electronics. System Designers and IC Engineers will be encouraged to: BUILD! Create the vision for ultra-thin possibilities. Put electronics into places and things never before possible with, prototypes, testing, reporting, and introducing new thin concepts. Reliability Leaders will be encouraged to: TEST! Update test procedures and standards to include physical deformations and then report and challenge the industry to improve. Universities will be called to: CREATE! Generate new physics/models associated with deformations, develop interconnect innovations and advance new materials. In general, the presentation makes the case that hardware matters – Let's build some new technology.

Escalating Challenges in Developing Complex Solutions for Next Generation Package and Interconnect Technologies

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 001306-001353
Author(s):  
Robert Darveaux
Keyword(s):  
Power Dissipation ◽  
Flip Chip ◽  
Cost Effective ◽  
Handheld Devices ◽  
Wafer Level ◽  
Higher Power ◽  
Complex Solutions ◽  
Exciting Time ◽  
Ic Package ◽  
Full Conversion

There are several application and device trends driving IC package development today. Among the most prevalent are:- Form factor reduction for handheld devices- Increased functionality requiring higher bandwidth- Higher power dissipation- Higher operating frequencies resulting in reduced electrical noise margins- Increased use of sensors- Full conversion to green material sets- Silicon node progression. These trends occur concurrently in many applications, which often results in conflicting requirements. In addition, the market continues to apply relentless pricing pressure on the supply chain. Hence, simple, cost-effective solutions are mandatory. This presentation will highlight packaging technology developments that address the device and application trends listed above. Several innovative packaging platforms will be discussed:- Copper pillar CSP and BGA- Through Mold Via Package on Package (TMV ® PoP)- Flip Chip Molded BGA (FCMBGA)- Wafer Level CSP- Through Silicon Via CSP and BGA. In each case a clear value proposition will be presented, along with key supporting data. It is truly an exciting time to be part of the industry solving complex packaging and interconnect challenges.

Thin Film Packaging Reinforcement for Overmolded MEMS

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 001095-001119
Author(s):  
Gillot Charlotte ◽  
Jean-Louis Pornin ◽  
Christophe Billard ◽  
Emannuelle Lagoute ◽  
Mihel Pellat ◽  
...  
Keyword(s):  
Thin Film ◽  
Flip Chip ◽  
Low Cost ◽  
Short Circuit ◽  
Cost Effective ◽  
Wafer Level ◽  
Silicon Area ◽  
Mechanical Constraints ◽  
Test Card ◽  
Manufacturing Technologies

Thin Film packaging (TFP) is now well known at CEA/LETI and mainly used as a protection for MEMS against degradation which can occur during back end processes: TFP is strong enough to endure the mechanical constraints due to grinding, handling and protects the device from water during the sawing step. Our TFP process is also compatible with under bump metallisation, balling and flip chip processes. The main advantages of our TFP is a very low lost of silicon area, a low cost process with 3 mask levels, and is performed on equipments commonly used in IC fab. In this paper we will speek about process improvement for a TFP overmolded. The thermo-mechanical constraints due to the standard overmolding step (100 bars and 200°C) are much more challenging for TFP: the cavity is about 5 μm high, the cap layer 2μm thick and the polymer plugging layer 6μm thick. So TFP needs to be reinforced to withstand these high constraints. Two processes using conventional IC manufacturing technologies have been developed at wafer level with two materials. 200μm and 500μm wide cavities with TFP were reinforced with these processes and first tested under pneumatically pressure at room temperature: in case of contact between the cap and the substrate, a short circuit is measured between one electrode on the substrate and another electrode behind the cap. Then, the same devices were overmolded at 75 bars and 100 bars at 185°C. In the same run, BAW resonators with TFP and one type of reinforcement were overmolded at 100 bars. The electrical performances of these resonators after overmolding fit very well to the modelling of the test card and are very good. This Compatibility between TFP and overmolding constraints could be a cost effective solution in MEMS packaging.

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