Hardness assurance and testing techniques for high resolution (12- to 16-bit) analog-to-digital converters

1995 ◽  
Vol 42 (6) ◽  
pp. 1681-1688 ◽  
Author(s):  
C.I. Lee ◽  
B.G. Rax ◽  
A.H. Johnston
Keyword(s):  
High Resolution ◽  
Analog To Digital Converters ◽  
Analog To Digital ◽  
Testing Techniques

Superconducting High-Resolution Low-Pass Analog-to-Digital Converters

2007 ◽  
Vol 17 (2) ◽  
pp. 442-445 ◽  
Author(s):  
I.V. Vernik ◽  
D.E. Kirichenko ◽  
T.V. Filippov ◽  
A.. Talalaevskii ◽  
A.. Sahu ◽  
...  
Keyword(s):  
High Resolution ◽  
Analog To Digital Converters ◽  
Analog To Digital ◽  
Low Pass

scholarly journals The Impact of Noise and Mismatch on SAR ADCs and a Calibratable Capacitance Array Based Approach for High Resolutions

2013 ◽  
Vol 59 (2) ◽  
pp. 161-167 ◽  
Author(s):  
Jan Henning Mueller ◽  
Sebastian Strache ◽  
Laurens Busch ◽  
Ralf Wunderlich ◽  
Stefan Heinen
Keyword(s):  
High Resolution ◽  
Successive Approximation ◽  
Analog To Digital Converters ◽  
Limiting Factor ◽  
Charge Redistribution ◽  
Small Unit ◽  
Analog To Digital ◽  
Field Calibration ◽  
Medium Speed ◽  
The Impact

Abstract This paper describes widely used capacitor structures for charge-redistribution (CR) successive approximation register (SAR) based analog-to-digital converters (ADCs) and analyzes their linearity limitations due to kT/C noise, mismatch and parasitics. Results of mathematical considerations and statistical simulations are presented which show that most widespread dimensioning rules are overcritical. For high-resolution CR SAR ADCs in current CMOS technologies, matching of the capacitors, influenced by local mismatch and parasitics, is a limiting factor. For high-resolution medium-speed CR SAR ADCs, a novel capacitance array based approach using in-field calibration is proposed. This architecture promises a high resolution with small unit capacitances and without expensive factory calibration as laser trimming.

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