Nanoscale Topography Characterization for Direct Bond Interconnect

2019 ◽  
Author(s):  
Bongsub Lee ◽  
Pawel Mrozek ◽  
Gill Fountain ◽  
John Posthill ◽  
Jeremy Theil ◽  
...  
Keyword(s):  
Direct Bond ◽  
Nanoscale Topography

Influence of systematically varied nanoscale topography on the morphology of epithelial cells

2003 ◽  
Vol 2 (2) ◽  
pp. 49-57 ◽  
Author(s):  
A. Andersson ◽  
J. Brink ◽  
U. Lidberg ◽  
D.S. Sutherland
Keyword(s):  
Epithelial Cells ◽  
Nanoscale Topography

Fe-Doped Zirconium Oxide Produced by Self-Sustained High-Temperature Synthesis:  Evidence for an Fe−Zr Direct Bond

1999 ◽  
Vol 121 (2) ◽  
pp. 301-307 ◽  
Author(s):  
Paolo Ghigna ◽  
Giorgio Spinolo ◽  
Umberto Anselmi-Tamburini ◽  
Filippo Maglia ◽  
Monica Dapiaggi ◽  
...  
Keyword(s):  
High Temperature ◽  
Zirconium Oxide ◽  
Temperature Synthesis ◽  
Direct Bond ◽  
High Temperature Synthesis

The Continued Adoption of ZiBond and DBI in Volume Applications

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 1-46
Author(s):  
Kathy Cook
Keyword(s):  
Intellectual Property ◽  
Direct Bond

Abstract not available. Outline: Company Background; Intellectual Property Status; Homogeneous Direct Bond (ZiBond) Technology; Hetergeneous Direct Bond (DBI) Technology; Wafer to Wafer (W2W) Applications; Implementation; and Summary

Low Temperature Direct Bond Technology for 3D Microelectronics Integration and Wafer Scale Packaging

2010 ◽  
Vol 2010 (1) ◽  
pp. 000015-000022
Author(s):  
Paul Enquist
Keyword(s):  
Low Temperature ◽  
Sensor Arrays ◽  
Cost Savings ◽  
Image Sensor ◽  
Network On Chip ◽  
Wafer Scale ◽  
Direct Bond ◽  
3D Network ◽  
On Chip ◽  
3D Volume

3D microelectronics integration and wafer scale packaging promise improvements in functional density and cost compared to conventional 2D microelectronics and packaging technologies. The realization of these improvements will require further adoption of 3D volume manufacturing process technologies. These process technologies will likely include through silicon via (TSV) and die or wafer bonding with and without 3D interconnect. Low temperature direct bond technologies have a number of inherent performance and cost advantages compared to other bonding technologies. This paper describes low temperature direct oxide bond technologies with and without a scalable 3D interconnect developed by Ziptronix and cost savings, performance and applications that will be enabled by adoption of these technologies. Enabled cost savings and performance include system or network-on-chip, system in package, and TSVs. Enabled applications include backside illuminated image sensors, micron-scale pitch vertically integrated image sensor arrays, 3D system-on-chip and 3D network-on-chip.

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