Progress in Fabrication and Test of Glass Interposer Substrates

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 001239-001258
Author(s):  
Aric Shorey ◽  
Scott Pollard
Keyword(s):  
Economies Of Scale ◽  
Functional Performance ◽  
Positive Impact ◽  
Coefficient Of Thermal Expansion ◽  
Electrical Characterization ◽  
Electrical Performance ◽  
Thin Glass ◽  
Reliability Performance ◽  
Downstream Processes ◽  
3D Applications

There is growing interest in applying glass as an interposer substrate for 2.5D/3D applications. Advantages of glass based solutions include significant opportunities for cost benefits by leveraging economies of scale as well as forming substrates at design thickness. A lot of work is being done to validate the value of glass as an interposer substrate. One important area is the electrical performance of glass relative to silicon. Because glass is an insulator, it is expected to have better electrical performance than silicon. Electrical characterization and electrical models demonstrate the advantages of the insulating properties of glass, and its positive impact on functional performance. Further advantages are anticipated in reliability performance, because of the ability to adjust thermal properties such as coefficient of thermal expansion (CTE) of glass. Progress in the ability to fabricate wafers and panels fully populated with through and blind holes has been reported. We describe the ability to leverage existing downstream processes such as via filling of both through and blind vias, as well as novel handling techniques to enable processing of thin glass. We also report progress in evaluating reliability through thermal cycle tests.

Glass Interposer Substrates: Fabrication, Characterization and Modeling

2013 ◽  
Vol 2013 (1) ◽  
pp. 000625-000630 ◽  
Author(s):  
Aric Shorey ◽  
Satish Chaparala ◽  
Scott Pollard ◽  
Garrett Piech ◽  
John Keech
Keyword(s):  
Economies Of Scale ◽  
Functional Performance ◽  
Positive Impact ◽  
Coefficient Of Thermal Expansion ◽  
Electrical Characterization ◽  
Electrical Performance ◽  
Patterned Wafers ◽  
Downstream Processes ◽  
3D Applications ◽  
Made In

There is growing interest in applying glass as a substrate for 2.5D/3D applications. Glass has many material properties that make it well suited for interposer substrates. Glass based solutions provide significant opportunities for cost reduction by leveraging economies of scale as well as forming substrates at design thickness. A lot of work is being done to validate the value of glass as an interposer substrate. One important area is the electrical performance of glass relative to silicon. Because glass is an insulator, an interposer made with glass should have better electrical performance than one made with silicon. Electrical characterization and electrical models confirm this advantage, and its positive impact on functional performance. Further advantages are anticipated in reliability, driven by the ability to tailor thermal properties such as coefficient of thermal expansion (CTE) of glass. Modeling results will be presented that show how the proper choice of CTE can significantly lower stack warpage. Additionally, significant progress has been made in the demonstration of glass interposer fabrication. Fully patterned wafers and panels with through holes and blind holes are being fabricated today. It is equally important to be able to demonstrate the ability to leverage existing downstream processes for metallization of these substrates. The ability to apply existing downstream processes to make functional glass interposers using both through and blind via technology will be presented.

Glass Substrates for Advanced Packaging

2014 ◽  
Vol 2014 (1) ◽  
pp. 000388-000392
Author(s):  
Aric Shorey ◽  
Scott Pollard
Keyword(s):  
Economies Of Scale ◽  
Functional Performance ◽  
Positive Impact ◽  
Cost Effective ◽  
Electrical Performance ◽  
Great Promise ◽  
Glass Substrates ◽  
The Status ◽  
Substantial Progress ◽  
Advanced Packaging

There has been substantial work done in the past few years to apply glass solutions for Advanced Packaging. Advantages of glass based solutions create significant opportunities by leveraging economies of scale, forming substrates at design thickness and leveraging thermal and electrical properties. A lot of work is being done to validate the value of glass as an interposer substrate. The ability to leverage both wafer and panel-based metallization strategies for filling glass vias has been shown. Transitioning these processes to cost-effectiveness and high throughput has shown great promise. The electrical performance of glass relative to silicon at high frequencies makes glass solutions very attractive, particularly in RF applications. Electrical models and characterization have demonstrated the advantages of the insulating properties of glass, and its positive impact on functional performance. Reliability tests show that glass solutions can meet device requirements. The substantial progress and readiness in these areas will be presented. Glass based solutions in panel format provide exciting and cost effective industry opportunities by leveraging economies of scale and glass forming technology. Existing technologies can be used to fill glass vias in a panel format, as well as apply redistribution layers. We will present the status of leveraging panel based technology to enable glass interposers.

Electrical Characterization on a High-Speed Wafer-Level Package

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001937-001962
Author(s):  
Kai Liu ◽  
YongTaek Lee ◽  
HyunTai Kim ◽  
MaPhooPwint Hlaing ◽  
Susan Park ◽  
...  
Keyword(s):  
High Speed ◽  
Unit Length ◽  
Ground Plane ◽  
Measurement Data ◽  
Electrical Characterization ◽  
Electrical Performance ◽  
Metal Loss ◽  
Signal Loss ◽  
Wafer Level ◽  
Wafer Level Package

In this paper, a 2-layer eWLB (embedded Wafer-Level BGA) is studied and its performance is compared with an equivalent 4-layer laminate package. Since eWLB package is processed by using lithographical method, design rules on width (W) and spacing (S) are much finer (usually 2–3 times finer) than those for laminate package. In other words, signal traces can be implemented in smaller fan-out regions. The smaller feature sizes for signal traces would end up with more metal loss per unit length. But as the signal traces can be implemented in smaller fan-out regions, overall trace-routing may be shorter, and equivalent insertion-loss may be achieved. In eWLB, the ground plane is closer to the signal traces. This actually helps to reduce cross-talk between wide I/O buses, as the electrical field is contained in a smaller region by the closer ground plane. Another key advantage from wafer-level package is a smoother metal surface, which greatly reduces the extra signal loss, due to surface-roughness effect, especially for higher-frequency and higher-speed applications. In addition, through-via structures for wafer-level package are typically 2–3 times smaller. This allows to implement power/ground planes in a more continuous way, achieving better resistance and inductance for power/ground nets. Overall electrical performance, which takes into account of all the impacts above, can be evaluated by signal-integrity analysis (E-diagram). Measurement data of a 2-layer eWLB package for a LPDDR application will be presented, which shows the comparable performance typically obtained from a 4-layer laminate package

Development of Substrates for Through Glass Vias

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 000832-000845 ◽  
Author(s):  
Aric Shorey ◽  
Scott Pollard
Keyword(s):  
Material Properties ◽  
Glass Composition ◽  
Coefficient Of Thermal Expansion ◽  
Cost Effective ◽  
High Volume ◽  
Chemical Durability ◽  
Thin Glass ◽  
Wide Range ◽  
Challenges And Opportunities ◽  
Substantial Progress

Through-substrate vias are critical for 3DS-IC integration. The choice of glass as an interposer substrate, TGV, present some interesting challenges and opportunities, making glass a compelling alternative to silicon. There are two primary challenges to begin building a precision interposer in thin glass. The first is high quality thin glass wafers (300 mm OD, thickness 0.05 to 0.10 mm, warp and TTV of 30 μm and 1 μm respectively). The second challenge is developing a process capable of providing small (5–10 μm) precision vias in a cost-effective way. “Glass” represents a large class of materials with a wide range of material properties. The first step in developing TGV is to identify the most appropriate glass composition for the application, which furthermore defines important properties such as coefficient of thermal expansion (CTE) and other mechanical properties, chemical durability and electrical properties. The manufacturing process used to develop the glass has a significant impact on quality and manufacturability. Fusion formed glass provides a solution for high volume manufacturing supply in an as-formed, ultra-thin, pristine glass manufactured to tight tolerances, and avoids the issues associated with polishing or thinning. The supply of 50 μm to 100 μm as-formed ultra-thin glass wafers can compare very favorably in cost relative to polished or thinned glass as well as thinned silicon wafer. While there are many technologies that have demonstrated vias in glass, challenges relating to via size and pitch, wafer strength and reliability remain to be resolved. However, substantial progress has been made to meet these challenges. Specific characterization data from some of these processes to demonstrate vias on the order of 10 μm diameter with a 100 μm glass thickness in alternative glass materials will be presented.

Leveraging Glass Properties for Advanced Packaging

2015 ◽  
Vol 2015 (1) ◽  
pp. 000370-000374
Author(s):  
A.B. Shorey ◽  
Y.J. Lu ◽  
G.A. Smith
Keyword(s):  
Coefficient Of Thermal Expansion ◽  
Cost Effective ◽  
High Frequencies ◽  
Glass Substrates ◽  
Glass Forming ◽  
Cost Structures ◽  
Advanced Packaging ◽  
Downstream Processes ◽  
Electrical Loss ◽  
Made In

Glass provides many opportunities for advanced packaging. The most obvious advantage is given by the material properties. As an insulator, glass has low electrical loss, particularly at high frequencies. The relatively high stiffness and ability to adjust the coefficient of thermal expansion gives advantages to manage warp in glass core substrates and bonded stacks for both through glass vias (TGV) and carrier applications. Glass also gives advantages for developing cost effective solutions. Glass forming processes allow the potential to form both in panel format as well as at thicknesses as low as 100 um, giving opportunities to optimize or eliminate current manufacturing methods. As the industry adopts glass solutions, significant advancements have been made in downstream processes such as glass handling and via/surface metallization. Of particular interest is the ability to leverage tool sets and processes for panel fabrication to enable cost structures desired by the industry. By utilizing the stiffness and adjustable CTE of glass substrates, as well as continuously reducing via size that can be made in a panel format, opportunities to manufacture glass TGV substrates in a panel format increase. We will provide an update on advancements in these areas as well as handling techniques to achieve desired process flows. We will also provide the latest demonstrations of electrical, thermal and mechanical reliability.

Development of G-Helix Structure as Off-Chip Interconnect

2004 ◽  
Vol 126 (2) ◽  
pp. 237-246 ◽  
Author(s):  
Qi Zhu ◽  
Lunyu Ma ◽  
Suresh K. Sitaraman
Keyword(s):  
Mechanical Performance ◽  
Coefficient Of Thermal Expansion ◽  
Mechanical Analysis ◽  
Organic Substrate ◽  
Electrical Performance ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Package Weight ◽  
Mechanical Compliance ◽  
Cte Mismatch

Microsystem packages continue to demand lower cost, higher reliability, better performance and smaller size. Compliant wafer-level interconnects show great potential for next-generation packaging. G-Helix, an electroplated compliant wafer-level chip-to-substrate interconnect can facilitate wafer-level probing as well as wafer-level packaging without the need for an underfill. The fabrication of the G-Helix interconnect is similar to conventional IC fabrication process and is based on electroplating and photolithography. G-Helix interconnect has good mechanical compliance in the three orthogonal directions and can accommodate the differential displacement induced by the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate. In this paper, we report the wafer-level fabrication of an area-arrayed G-Helix interconnects. The geometry effect on the mechanical compliance and electrical parasitics of G-Helix interconnects have been studied. Thinner and narrower arcuate beams with larger radius and taller post are found to have better mechanical compliance. However, it is also found that structures with excellent mechanical compliance may not have good electrical performance. Therefore, a trade off is needed. Using response surface methodology (RSM), an optimization has been done. Furthermore, reliability of the optimized G-helix interconnects in a silicon-on-organic substrate assembly has been assessed, which includes the package weight and thermo-mechanical analysis. The pitch size effect on the electrical and mechanical performance of G-Helix interconnects has also been studied.

A Heterogeneous Array of Off-Chip Interconnects for Optimum Mechanical and Electrical Performance

2007 ◽  
Vol 129 (4) ◽  
pp. 460-468 ◽  
Author(s):  
Karan Kacker ◽  
Thomas Sokol ◽  
Wansuk Yun ◽  
Madhavan Swaminathan ◽  
Suresh K. Sitaraman
Keyword(s):  
Flip Chip ◽  
Dielectric Material ◽  
Coefficient Of Thermal Expansion ◽  
Semiconductor Industry ◽  
Organic Substrate ◽  
Electrical Performance ◽  
Integrative Approach ◽  
Wafer Level ◽  
Target Values ◽  
Low K

Demand for off-chip bandwidth has continued to increase. It is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors that by the year 2015, the chip-to-substrate area-array input-output interconnects will require a pitch of 80 μm. Compliant off-chip interconnects show great potential to address these needs. G-Helix is a lithography-based electroplated compliant interconnect that can be fabricated at the wafer level. G-Helix interconnects exhibit excellent compliance in all three orthogonal directions, and can accommodate the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate without requiring an underfill. Also, these compliant interconnects are less likely to crack or delaminate the low-k dielectric material in current and future integrated circuits. The interconnects are potentially cost effective because they can be fabricated in batch at the wafer level and using conventional wafer fabrication infrastructure. In this paper, we present an integrative approach, which uses interconnects with varying compliance and thus varying electrical performance from the center to the edge of the die. Using such a varying geometry from the center to the edge of the die, the system performance can be tailored by balancing electrical requirements against thermomechanical reliability concerns. The test vehicle design to assess the reliability and electrical performance of the interconnects is also presented. Preliminary fabrication results for the integrative approach are presented and show the viability of the fabrication procedure. The results from reliability experiments of helix interconnects assembled on an organic substrate are also presented. Initial results from the thermal cycling experiments are promising. Results from mechanical characterization experiments are also presented and show that the out-of-plane compliance exceeds target values recommended by industry experts. Finally, through finite element analysis simulations, it is demonstrated that the die stresses induced by the compliant interconnects are an order of magnitude lower than the die stresses in flip chip on board (FCOB) assemblies, and hence the compliant interconnects are not likely to crack or delaminate low-k dielectric material.

scholarly journals Structural Characterization of Movpe Grown Algan/Gan for Hemt Formation

2018 ◽  
Vol 57 (1) ◽  
pp. 72-81 ◽  
Author(s):  
V.N. Popok ◽  
T.S. Aunsborg ◽  
R.H. Godiksen ◽  
P.K. Kristensen ◽  
R.R. Juluri ◽  
...  
Keyword(s):  
Electrical Characterization ◽  
Charge Carrier Concentration ◽  
Electrical Performance ◽  
Clear Understanding ◽  
Si Substrates ◽  
Transfer Of Technology ◽  
Dislocation Densities ◽  
Unusual Phenomenon ◽  
Aln Buffer

Abstract Results on structural, compositional, optical and electrical characterization of MOVPE grown AlGaN/GaN heterostructures with focus on understanding how the AlN buffer synthesis affects the top films are reported. The study demonstrates very good correlation between different methods providing a platform for reliable estimation of crystalline quality of the AlGaN/GaN structures and related to that electrical performance which is found to be significantly affected by threading dislocations (TD): higher TD density reduces the electron mobility while the charge carrier concentration is found to be largely unchanged. The attempt to vary the ammonia flow during the AlN synthesis is found not to affect the film composition and dislocation densities in the following heterostructures. An unusual phenomenon of considerable diffusion of Ga from the GaN film into the AlN buffer is found in all samples under the study. The obtained results are an important step in optimization of AlGaN/GaN growth towards the formation of good quality HEMT structures on sapphire and transfer of technology to Si substrates by providing clear understanding of the role of synthesis parameter on structure and composition of the films.

Analysis of Business Development Strategy Straw Mushroom Raw Material Empty Fruit Bunch in Lampung Province

2020 ◽  
Vol 17 (9) ◽  
pp. 4710-4714
Author(s):  
Sarono ◽  
Eddy Irsan Siregar
Keyword(s):  
Development Strategy ◽  
Palm Oil ◽  
Economies Of Scale ◽  
Positive Impact ◽  
Business Development ◽  
Transportation Costs ◽  
Raw Material ◽  
Empty Fruit Bunch ◽  
Business Unit ◽  
Straw Mushroom

In Lampung, many businesses produce mushrooms made from empty fruit bunch (EFB) palm oil, this has a positive impact on companies and communities around the company. The objective of the research is to identify the strengths, weaknesses, opportunities, and threats of the EFB standard mushroom business and the analysis of its development strategy in Lampung Province. The result of the research shows that (1) the development of mushroom industry made from EFB in Lampung Province has the strength of raw material available in large quantities and easily obtained, while the weakness is mushroom is a product that is easily damaged and untreated mushroom waste; (2) the odds are that the need for food mushrooms is still high and tends to increase, while the threat is increasing production and transportation costs and uncontrolled extreme weather; and (3) the main priority strategy for the large business unit is the development of new mushroom processing business and the modernization of mushroom making technology, while for the small and beginner business unit is to encourage business development to reach economies of scale.

Underfill Assessments and Validations for Low-k FCBGA

2006 ◽  
Author(s):  
Nicholas Kao ◽  
Jeng Yuan Lai ◽  
Jase Jiang ◽  
Yu Po Wang ◽  
C. S. Hsiao
Keyword(s):  
Finite Element ◽  
High Speed ◽  
Flip Chip ◽  
Failure Modes ◽  
Solder Bump ◽  
Material Selection ◽  
Coefficient Of Thermal Expansion ◽  
Electrical Performance ◽  
Low K ◽  
Underfill Material

With the trend of electronic consumer product toward more functionality, high performance and miniaturization, IC chip is required to deliver more I/Os signals and better electrical characteristics under same package form factor. Thus, Flip Chip BGA (FCBGA) package was developed to meet those requirements offering better electrical performance, more I/O pins accommodation and high transmission speed. For high-speed application, the low dielectric constant (low-k) material that can effectively reduce the signal delays is extensively used in IC chips. However, the low-k material possesses fragile mechanical property and high coefficient of thermal expansion (CTE) compared with silicon chip, which raises the reliability concerns of low-k material integrated into IC chip. The typical reliability failure modes are low-k layer delamination and bump crack under temperature loading during assembly and reliability test. Delamination is occurred in the interface between low-k dielectric layers and underfill material at chip corner. Bump crack is at Under Bump Metallization (UBM) corner. Thus, the adequate underfill material selection becomes very important for both solder bump and low-k chips [1]. This paper mainly characterized FCBGA underfill materials to guide the adequate candidates to prevent failures on low-k chip and solder bump. Firstly, test vehicle was a FCBGA package with heat spreader and was investigated the thermal stress by finite element models. In order to analyze localized low-k structures, sub-modeling technique is used for underfill characterizations. Then, the proper underfill candidates picked from modeling results were experimentally validated by reliability tests. Finally, various low-k FCBGA package structures were also studied with same finite element technique.

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