Electrical-Thermal-Reliability Co-Design for TSV-Based 3D-ICs

2015 ◽  
Author(s):  
Tiantao Lu ◽  
Ankur Srivastava
Keyword(s):  
Mechanical Stress ◽  
Electrical Performance ◽  
Mechanical Reliability ◽  
Thermal Reliability ◽  
Conduction Path ◽  
Placement Problem ◽  
Thermal Profile ◽  
3D Ic ◽  
3D Ics ◽  
Simulation Based

This paper presents an electrical-thermal-reliability co-design technique for TSV-based 3D-ICs. Although TSV-based 3D-IC shows significant electrical performance improvement compared to traditional 2D circuit, researchers have reported strong electromigration (EM) in TSVs, which is induced by the thermal mechanical stress and the local temperature hotspot. We argue that rather than addressing 3D-IC’s EM issue after the IC designing phase, the designer should be aware of the circuit’s thermal and EM properties during the IC designing phase. For example, one should be aware that the TSVs establish vertical heat conduction path thus changing the chip’s thermal profile and also produce significant thermal mechanical stress to the nearby TSVs, which deteriorates other TSV’s EM reliability. Therefore, the number and location of TSVs play a crucial role in deciding 3D-IC’s electrical performance, changing its thermal profile, and affecting its EM-reliability. We investigate the TSV placement problem, in order to improve 3D-IC’s electrical performance and enhance its thermal-mechanical reliability. We derive and validate simple but accurate thermal and EM models for 3D-IC, which replace the current employed time-consuming finite-element-method (FEM) based simulation. Based on these models, we propose a systematic optimization flow to solve this TSV placement problem. Results show that compared to conventional performance-centered technique, our design methodology achieves 3.24x longer EM-lifetime, with only 1% performance degradation.

Cost Effective Production of Glass Interposers for 3D ICs Using APEX(TM) Glass Ceramic

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 001269-001290
Author(s):  
Jeb H. Flemming ◽  
Kevin Dunn ◽  
James Gouker ◽  
Carrie Schmidt
Keyword(s):  
Glass Ceramic ◽  
Cost Effective ◽  
Electrical Performance ◽  
Sensitive Material ◽  
Aspect Ratios ◽  
3D Ics ◽  
Simple Processing ◽  
Micron Diameter ◽  
On Chip ◽  
Processing Steps

The most singular focus of the electronics industry during the last 50 years has been to miniaturize ICs by miniaturization of transistors and on-chip interconnections. Two major problems are foreseen with this approach; electrical leakage and lack of improved electrical performance beyond 16nm. As a result, industry is transitioning from the current SOC-based approach to a through-silicon-via (TSV) based 3D IC-stacked approach. However, a major challenge remains; these 3D ICs need to be interconnected to other ICs with a much higher number of I/Os than are available with current ceramic or organic interposers. While silicon interposers currently in development can provide these high I/Os, they cannot do so at low enough cost. In this talk, we will present on our efforts in glass interposers fabrication. Glass interposers possess many advantages over silicon interposers including: cost, production time, and scale. Life MicroFab's APEX™ Glass ceramic is a photo-sensitive material used to create high density arrays of through glass vias (TGVs) using three simple processing steps: exposure, baking, and etching. To date, we have been successful in producing large arrays of 12 micron diameter TGVs, with 14 micron center-to-center pitchs, in 125 micron thick APEX™ Glass ceramic. We will present (1) on our efforts producing high aspect ratio TGVs in thin (500-250 micron) and ultra thin (250-75 micron) APEX™ Glass ceramic wafers, (2) maximum TGV aspect ratios, and (3) TGV fidelity and limits of manufacturing.

Design and Robustness of Quilt Packaging Superconnect

2012 ◽  
Vol 2012 (1) ◽  
pp. 000524-000530
Author(s):  
M. Ashraf Khan ◽  
Jason M. Kulick ◽  
Alfred M. Kriman ◽  
Gary H. Bernstein
Keyword(s):  
Thermal Cycling ◽  
High Speed ◽  
Low Cycle Fatigue ◽  
Simulation Models ◽  
Electrical Performance ◽  
Cycle Fatigue ◽  
Signal Delay ◽  
Thermal Reliability ◽  
Simulation Results ◽  
Quilt Packaging

Quilt Packaging (QP) is a novel high-speed superconnect (i.e. direct interchip interconnect), developed to improve electrical performance — signal delay, power loss, etc. Ultrahigh bandwidth has already been demonstrated for QP, but its unique structure requires thermal reliability issues to be studied. To this end, simulation models were developed to study the robustness of QP. QP structures were fabricated, and thermal cycling tests were performed focusing on the reliability for various shapes of nodules, the basic physical interconnect unit of QP. Simulations were performed to determine stress over a range of temperatures and estimate low cycle fatigue lifetimes. Simulations considered two types of solder and several adhesives. Thermal cycling experiments indicate that QP provides a robust structure, in agreement with the simulation results.

Review and Projections of Integrated Cooling Systems for Three-Dimensional Integrated Circuits

2014 ◽  
Vol 136 (2) ◽  
Author(s):  
Satish G. Kandlikar
Keyword(s):  
Hot Spots ◽  
Heat Dissipation ◽  
Cooling System ◽  
Mechanical Design ◽  
Heat Fluxes ◽  
Electrical Performance ◽  
Channel Height ◽  
Cooling Systems ◽  
3D Ic ◽  
Pressure Drops

In an effort to increase processor speeds, 3D IC architecture is being aggressively pursued by researchers and chip manufacturers. This architecture allows extremely high level of integration with enhanced electrical performance and expanded functionality, and facilitates realization of VLSI and ULSI technologies. However, utilizing the third dimension to provide additional device layers poses thermal challenges due to the increased heat dissipation and complex electrical interconnects among different layers. The conflicting needs of the cooling system requiring larger flow passage dimensions to limit the pressure drop, and the IC architecture necessitating short interconnect distances to reduce signal latency warrant paradigm shifts in both of their design approach. Additional considerations include the effects due to temperature nonuniformity, localized hot spots, complex fluidic connections, and mechanical design. This paper reviews the advances in 3D IC cooling in the last decade and provides a vision for codesigning 3D IC architecture and integrated cooling systems. For heat fluxes of 50–100 W/cm2 on each side of a chip in a 3D IC package, the current single-phase cooling technology is projected to provide adequate cooling, albeit with high pressure drops. For future applications with coolant surface heat fluxes from 100 to 500 W/cm2, significant changes need to be made in both electrical and cooling technologies through a new level of codesign. Effectively mitigating the high temperatures surrounding local hot spots remains a challenging issue. The codesign approach with circuit, software and thermal designers working together is seen as essential. The through silicon vias (TSVs) in the current designs place a stringent limit on the channel height in the cooling layer. It is projected that integration of wireless network on chip architecture could alleviate these height restrictions since the data bandwidth is independent of the communication lengths. Microchannels that are 200 μm or larger in depth are expected to allow dissipation of large heat fluxes with significantly lower pressure drops.

Fast Thermal Analysis of Vertically Integrated Circuits (3-D ICs) Using Power Blurring Method

2009 ◽  
Author(s):  
Je-Hyoung Park ◽  
Ali Shakouri ◽  
Sung-Mo Kang
Keyword(s):  
Integrated Circuits ◽  
Power Dissipation ◽  
Three Dimensional ◽  
Computation Time ◽  
Maximum Error ◽  
3D Ic ◽  
Additional Advantage ◽  
3D Ics ◽  
Ic Technology ◽  
Power Blurring

CMOS VLSI technology has been facing various technical challenges as the feature sizes scale down. To overcome the challenges imposed by the shrink of the conventional on-chip interconnect system in IC chips, alternative interconnect technologies are being developed: one of them is three dimensional chips (3D ICs). Even though 3D IC technology is a promising solution for interconnect bottlenecks, thermal issues can be exacerbated. Thermal-aware design and optimization will be more critical in 3D IC technology than conventional planar IC technology, and hence accurate temperature profiles of each active layer will become very important. In 3D ICs, temperature profile of one layer depends not only on its own power dissipation but also on the heat transferred from other layers. Thus, thermal considerations for 3D ICs need to be done in a holistic manner even if each layer can be designed and fabricated individually. Conventional grid-based temperature computation methods are accurate but are computationally expensive, especially for 3D ICs. To increase computational efficiency, we developed a matrix convolution technique, called Power Blurring (PB) for 3D ICs. The temperature resulting from any arbitrary power dissipation in each layer of the 3D chip can be computed quickly. The PB method has been validated against commercial FEA software, ANSYS. Our method yields good results with maximum error less than 2% for various case studies and reduces the computation time by a factor of ∼ 60. The additional advantage is the possibility to evaluate different power dissipation profiles without the need to re-mesh the whole 3D chip structure.

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