Development and electrical investigation of novel fine-pitch Cu/Sn pad bumping using ultra- thin buffer layer technique in 3D integration

2015 ◽  
Author(s):  
Yu-Sheng Hsieh ◽  
Yao-Jen Chang ◽  
Kuan-Neng Chen
Keyword(s):  
Buffer Layer ◽  
3D Integration ◽  
Electrical Investigation ◽  
Fine Pitch ◽  
Layer Technique

An Application of the Buffer Layer Technique to Computations of Flow in Turbomachinery

2004 ◽  
pp. 299-309 ◽  
Author(s):  
Franco Magagnato ◽  
Jaroslaw Rachwalski ◽  
Martin Gabi
Keyword(s):  
Buffer Layer ◽  
Layer Technique

Bonding Technologies for 3D integration

2015 ◽  
Vol 2015 (1) ◽  
pp. 000231-000234
Author(s):  
Sascha Lohse ◽  
Alexander Wollanke
Keyword(s):  
Flip Chip ◽  
Process Technology ◽  
3D Integration ◽  
Test Procedures ◽  
Fine Pitch ◽  
Ic Packaging ◽  
Die Stacking ◽  
3D Packaging ◽  
Small Bump ◽  
Suitable Process

Tougher requirements related to the request for smaller, lighter and multi-functional electronic devices impose increased demands on IC packaging. Ever more complex circuitry, fine pitch and micro bump designs and die stacking are examples of how the industry meets these demands. Finding a suitable process technology for 3D packaging can be a challenge. This paper provides information about various connection methods predominantly used in today's 3D packaging. In comprehensive trials, various dies characterized by high bump count (up to 143,000), fine pitch (down to 25 μm) and small bump diameter (down to 13 μm) were placed on a substrate using a semi-automated flip chip bonder. This whitepaper describes test procedures for different 3D integration technologies and presents utilized process parameters and results.

Scaling Challenges of Semiconductor Packaging in the Era of Big Data

2013 ◽  
Vol 2013 (1) ◽  
pp. 000402-000407 ◽  
Author(s):  
Yasumitsu Orii ◽  
Akihiro Horibe ◽  
Kazushige Toriyama ◽  
Keiji Matsumoto ◽  
Hirokazu Noma ◽  
...  
Keyword(s):  
Big Data ◽  
Material Selection ◽  
Organic Substrate ◽  
Critical Element ◽  
3D Integration ◽  
Technology Innovations ◽  
Fine Pitch ◽  
3D Chip Stacking ◽  
Semiconductor Packaging ◽  
Underfill Material

In advent of multimedia, social media and Internet of Things, our world is exploding with enormous amount of data, so-called Big Data. The use of Big Data provides us with opportunities to bring solutions and innovations to variety of industries such as healthcare, energy, banking and automotive. On the other hand, the computing requirement to analyze this large volume of data is becoming higher than ever. The exascale computing is required in the Era of Big Data. In order to achieve this demand, further technology innovations for package scaling such as 3D-IC with TSV (through silicon via) are needed. The fine pitch die-to-die interconnection is a key element in increasing the total bandwidth in 3D integration. The important technologies in 3D integration include micro-bumping, thermally enhanced underfill materials and advanced interposers. Material selection for reliable fine-pitch interconnection has become a critical challenge in 3D chip stacking. Underfill material in die-to-die device is also a critical element in reducing total packaging stress and in enhancing vertical thermal conductivity. Low CTE high-density organic substrate is an emerging technology for 2.5D structure.

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