Carbon Nanofibers (CNF) for enhanced solder-based nano-scale integration and on-chip interconnect solutions

2014 ◽  
Author(s):  
V. Desmaris ◽  
A. M. Saleem ◽  
S. Shafiee ◽  
J. Berg ◽  
M. S. Kabir ◽  
...  
Keyword(s):  
Carbon Nanofibers ◽  
Nano Scale ◽  
On Chip ◽  
Scale Integration

Nano-Scale Hydroxyapatite Coating on Macroscopic Silica Fiber Using Carbon Nanofibers as Templates

2008 ◽  
Vol 81 (3) ◽  
pp. 380-386 ◽  
Author(s):  
Qiang Wu ◽  
Hitoshi Ogihara ◽  
Hisaichiro Uchida ◽  
Masahiro Sadakane ◽  
Yoshinobu Nodasaka ◽  
...  
Keyword(s):  
Carbon Nanofibers ◽  
Hydroxyapatite Coating ◽  
Silica Fiber ◽  
Nano Scale

A High Q Gm-C Filter with On-Chip Automatic Tuning Circuit Implemented in Nano-Scale CMOS Process

2014 ◽  
Vol 6 (9) ◽  
pp. 856-860
Author(s):  
Xiao Fei Kuang ◽  
Chenxu Guo ◽  
Yuhua Cheng ◽  
Hengyi Wang
Keyword(s):  
Automatic Tuning ◽  
Cmos Process ◽  
Nano Scale ◽  
Tuning Circuit ◽  
On Chip

Nano-Scale Deposition of Hydroxyapatite on Bioactive and Bioinert Fibers Using Carbon Nanofibers as Templates

2011 ◽  
Vol 236-238 ◽  
pp. 2122-2125 ◽  
Author(s):  
Qiang Wu ◽  
Masahiro Sadakane ◽  
Hitoshi Ogihara ◽  
Wataru Ueda
Keyword(s):  
Carbon Nanofibers ◽  
Vapor Deposition ◽  
Fiber Surface ◽  
Chemical Vapor ◽  
Silica Fiber ◽  
Alumina Fiber ◽  
Nano Scale ◽  
Uniform Deposition ◽  
Scale Deposition ◽  
Better Than

The synthesis of nano-scale hydroxyapatite (HAp) could be achieved by using carbon nanofibers (CNFs) as templates. It was shown that both silica fiber and alumina fiber are suitable substrates for the growth of CNFs templates by chemical vapor deposition (CVD) technique. It turned out that the resulting CNFs could act as promising and effective templates for nano-scale deposition of HAp on the fiber surface. However, CNFs obtained from silica fiber performed better than those grown from alumina fiber for uniform deposition of HAp on the surface.

Self-Adaptive SoCs for Dependability

2014 ◽  
pp. 1-21
Author(s):  
Liang Guang ◽  
Juha Plosila ◽  
Hannu Tenhunen
Keyword(s):  
Large Scale ◽  
Future Research ◽  
Great Promise ◽  
Primary Concern ◽  
Technology Scaling ◽  
Computing Paradigm ◽  
Large Scale Integration ◽  
On Chip ◽  
Scale Integration ◽  
Self Adaptive

Dependability is a primary concern for emerging billion-transistor SoCs (Systems-on-Chip), especially when the constant technology scaling introduces an increasing rate of faults and errors. Considering the time-dependent device degradation (e.g. caused by aging and run-time voltage and temperature variations), self-adaptive circuits and architectures to improve dependability is promising and very likely inevitable. This chapter extensively surveys existing works on monitoring, decision-making, and reconfiguration addressing different dependability threats to Very Large Scale Integration (VLSI) chips. Centralized, distributed, and hierarchical fault management, utilizing various redundancy schemes and exploiting logical or physical reconfiguration methods, are all examined. As future research directions, the challenge of integrating different error management schemes to account for multifold threats and the great promise of error resilient computing are identified. This chapter provides, for chip designers, much needed insights on applying a self-adaptive computing paradigm to approach dependability on error-prone, cost-sensitive SoCs.

scholarly journals Genetic Algorithm-based thermal uniformity–aware X-filling to reduce peak temperature during testing

2018 ◽  
Vol 51 (7-8) ◽  
pp. 235-242 ◽  
Author(s):  
Arulmurugan Azhaganantham ◽  
Murugesan Govindasamy
Keyword(s):  
Genetic Algorithm ◽  
Power Consumption ◽  
Power Distribution ◽  
Large Scale ◽  
Heat Dissipation ◽  
Peak Temperature ◽  
Heating Event ◽  
Large Scale Integration ◽  
On Chip ◽  
Scale Integration

High temperature occurs in testing of complex System-on-Chip designs and it may become a critical concern to be carefully taken into account with continual development in Very Large Scale Integration technology. Peak temperature significantly affects the reliability and the performance of the chip. So it is essential to minimize the peak temperature of the chip. Heat generation by power consumption and heat dissipation to the surrounding blocks are the two prominent factors for the peak temperature. Power consumption can be minimized by a careful mapping of don’t cares in precomputed test set. However, it does not provide the solution to peak temperature minimization because the non-uniformity in spatial power distribution may create localized heating event called “hotspot.” The peak temperature on the hotspot is minimized by Genetic Algorithm–based don’t care filling technique that reduces the non-uniformity in spatial power distribution within the circuit under test while maintaining the overall power consumption at a lower level. Experimental results on ISCAS89 benchmark circuits demonstrate that 6%–28% peak temperature reduction can be achieved.

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