An accurate on-chip design estimation for mitigating EMI effects in a large-scale integration chip

2015 ◽  
Author(s):  
Sungwook Moon ◽  
Jinho Kim ◽  
Jihyun Lee ◽  
Taeyong Kim ◽  
Kyongho Kim
Keyword(s):  
Large Scale ◽  
Chip Design ◽  
Large Scale Integration ◽  
On Chip ◽  
Scale Integration

System-on-Chip Design of the Whirlpool Hash Function

2008 ◽  
pp. 256-270
Author(s):  
Paris Kitsos
Keyword(s):  
Hash Function ◽  
High Speed ◽  
Large Scale ◽  
System On Chip ◽  
Security Level ◽  
Chip Design ◽  
Silicon Area ◽  
Large Scale Integration ◽  
On Chip ◽  
Scale Integration

In this chapter, a system-on-chip design of the newest powerful standard in the hash families, named Whirlpool, is presented. With more details an architecture and two very large-scale integration (VLSI) implementations are presented. The first implementation is suitable for high speed applications while the second one is suitable for applications with constrained silicon area resources. The architecture permits a wide variety of implementation tradeoffs. Different implementations have been introduced and each specific application can choose the appropriate speed-area, trade-off implementation. The implementations are examined and compared in the security level and in the performance by using hardware terms. Whirlpool with RIPEMD, SHA-1, and SHA-2 hash functions are adopted by the International Organization for Standardization (ISO/IEC, 2003) 10118-3 standard. The Whirlpool implementations allow fast execution and effective substitution of any previous hash families’ implementations in any cryptography application.

Self-Adaptive SoCs for Dependability

2014 ◽  
pp. 1-21
Author(s):  
Liang Guang ◽  
Juha Plosila ◽  
Hannu Tenhunen
Keyword(s):  
Large Scale ◽  
Future Research ◽  
Great Promise ◽  
Primary Concern ◽  
Technology Scaling ◽  
Computing Paradigm ◽  
Large Scale Integration ◽  
On Chip ◽  
Scale Integration ◽  
Self Adaptive

Dependability is a primary concern for emerging billion-transistor SoCs (Systems-on-Chip), especially when the constant technology scaling introduces an increasing rate of faults and errors. Considering the time-dependent device degradation (e.g. caused by aging and run-time voltage and temperature variations), self-adaptive circuits and architectures to improve dependability is promising and very likely inevitable. This chapter extensively surveys existing works on monitoring, decision-making, and reconfiguration addressing different dependability threats to Very Large Scale Integration (VLSI) chips. Centralized, distributed, and hierarchical fault management, utilizing various redundancy schemes and exploiting logical or physical reconfiguration methods, are all examined. As future research directions, the challenge of integrating different error management schemes to account for multifold threats and the great promise of error resilient computing are identified. This chapter provides, for chip designers, much needed insights on applying a self-adaptive computing paradigm to approach dependability on error-prone, cost-sensitive SoCs.

scholarly journals Genetic Algorithm-based thermal uniformity–aware X-filling to reduce peak temperature during testing

2018 ◽  
Vol 51 (7-8) ◽  
pp. 235-242 ◽  
Author(s):  
Arulmurugan Azhaganantham ◽  
Murugesan Govindasamy
Keyword(s):  
Genetic Algorithm ◽  
Power Consumption ◽  
Power Distribution ◽  
Large Scale ◽  
Heat Dissipation ◽  
Peak Temperature ◽  
Heating Event ◽  
Large Scale Integration ◽  
On Chip ◽  
Scale Integration

High temperature occurs in testing of complex System-on-Chip designs and it may become a critical concern to be carefully taken into account with continual development in Very Large Scale Integration technology. Peak temperature significantly affects the reliability and the performance of the chip. So it is essential to minimize the peak temperature of the chip. Heat generation by power consumption and heat dissipation to the surrounding blocks are the two prominent factors for the peak temperature. Power consumption can be minimized by a careful mapping of don’t cares in precomputed test set. However, it does not provide the solution to peak temperature minimization because the non-uniformity in spatial power distribution may create localized heating event called “hotspot.” The peak temperature on the hotspot is minimized by Genetic Algorithm–based don’t care filling technique that reduces the non-uniformity in spatial power distribution within the circuit under test while maintaining the overall power consumption at a lower level. Experimental results on ISCAS89 benchmark circuits demonstrate that 6%–28% peak temperature reduction can be achieved.

Porous low dielectric constant materials for microelectronics

2005 ◽  
Vol 364 (1838) ◽  
pp. 201-215 ◽  
Author(s):  
Mikhail R Baklanov ◽  
Karen Maex
Keyword(s):  
Dielectric Constant ◽  
High Speed ◽  
Large Scale ◽  
Low Dielectric Constant ◽  
Low Dielectric ◽  
Large Scale Integration ◽  
The Subject ◽  
On Chip ◽  
Scale Integration ◽  
Selection Of

Materials with a low dielectric constant are required as interlayer dielectrics for the on-chip interconnection of ultra-large-scale integration devices to provide high speed, low dynamic power dissipation and low cross-talk noise. The selection of chemical compounds with low polarizability and the introduction of porosity result in a reduced dielectric constant. Integration of such materials into microelectronic circuits, however, poses a number of challenges, as the materials must meet strict requirements in terms of properties and reliability. These issues are the subject of the present paper.

Overview Of Process Integration Issues For Low K Dielectrics

1998 ◽  
Vol 511 ◽  
Author(s):  
R. H. Havemann ◽  
M. K. Jain ◽  
R. S. List ◽  
A. R. Ralston ◽  
W-Y. Shih ◽  
...  
Keyword(s):  
Large Scale ◽  
Process Integration ◽  
Functional Integration ◽  
Dielectric Materials ◽  
Limiting Factor ◽  
Large Scale Integration ◽  
On Chip ◽  
Scale Integration ◽  
Rc Delay ◽  
Low K

ABSTRACTThe era of silicon Ultra-Large-Scale-Integration (ULSI) has spurred an everincreasing level of functional integration on-chip, driving a need for greater circuit density and higher performance. While traditional transistor scaling has thus far met this challenge, interconnect scaling has become the performance-limiting factor for new designs. Both interconnect resistance and capacitance play key roles in overall performance, but modeling simulations have highlighted the importance of reducing parasitic capacitance to manage crosstalk, power dissipation and RC delay. New dielectric materials with lower permittivity (k) are needed to meet this challenge. This paper summarizes the process integration and reliability issues associated with the use of novel low k materials in multilevel interconnects.

scholarly journals Critical couplings in topological-insulator waveguide-resonator systems observed in elastic waves

2020 ◽  
Author(s):  
Si-Yuan Yu ◽  
Cheng He ◽  
Xiao-Chen Sun ◽  
Hong-Fei Wang ◽  
Ji-Qian Wang ◽  
...  
Keyword(s):  
Topological Insulator ◽  
Large Scale ◽  
Spectral Characteristics ◽  
Waveguide Resonator ◽  
Incoming Wave ◽  
Large Scale Integration ◽  
Core Components ◽  
Waveguide Ring ◽  
On Chip ◽  
Scale Integration

Abstract Waveguides and resonators are core components in the large-scale integration of electronics, photonics, and phononics, both in existing and future scenarios. In certain situations, there is critical coupling of the two components; i.e. no energy passes through the waveguide after the incoming wave couples into the resonator. The transmission spectral characteristics resulting from this phenomenon are highly advantageous for signal filtering, switching, multiplexing, and sensing. In the present study, adopting an elastic-wave platform, we introduce topological insulator (TI), a remarkable achievement in condensed matter physics over the past decade, into a classical waveguide-ring-resonator configuration. Along with basic similarities with classical systems, a TI system has important differences and advantages, mostly owing to the spin-momentum locked transmission states at the TI boundaries. As an example, a two-port TI waveguide resonator can fundamentally eliminate upstream reflections while completely retaining useful transmission spectral characteristics, and maximize the energy in the resonator, with possible applications being novel signal processing, gyro/sensing, lasering, energy harvesting, and intense wave–matter interactions, using phonons, photons, or even electrons. The present work further enhances the confidence of using topological protection for practical device performance and functionalities, especially considering the crucial advantage of introducing (pseudo)spins to existing conventional configurations. More in-depth research on advancing phononics/photonics, especially on-chip, is foreseen.

Does 0.1 Micron = MACH 1?

1995 ◽  
Vol 380 ◽  
Author(s):  
R. Fabian Pease
Keyword(s):  
High Performance ◽  
Large Scale ◽  
State Of The Art ◽  
Commercial Use ◽  
Optical Projection ◽  
Large Scale Integration ◽  
On Chip ◽  
Scale Integration ◽  
The Cost ◽  
The Military

ABSTRACTThe drive to increasingly higher density ultra-large-scale-integration (ULSI) (of electronic circuits) is fuelled primarily by cost; on-chip interconnects are far cheaper than the less dense offchip interconnects. At the same time the escalating cost of an IC factory (‘fab’) is making headlines as it goes through $1B and a large part of this escalation is the cost of high performance lithography tools. The lithographic technology to go below 0.1μm will almost certainly be very different from an extension of today's optical projection and the cost of replacing today's technology will be enormous. A second drawback to higher density is the resistance of narrow interconnects. As a result some people have suggested that this situation is analogous to that of airliner speed which increased over a period of thirty years from about 100 mph to close to 600 mph but has not increased in the last 35 years. Still faster speed was technically possible, and hence was pursued by the military, but is uneconomical for most commercial use. Current technology might take us to 0.1μm which will probably be state of the art 10 years hence so technologies for replacing optical lithography e.g. scanned arrays of proximal probes should be researched now. Other challenges include how to achieve useful interconnect networks employing 50 nm features.

scholarly journals Upscaling of pneumatic membrane valves for the integration of 3D cell cultures on chip

Lab on a Chip ◽  
2021 ◽  
Author(s):  
Nina Compera ◽  
Scott Atwell ◽  
Johannes Wirth ◽  
Bernhard Wolfrum ◽  
Matthias Meier
Keyword(s):  
Cell Culture ◽  
Cell Cultures ◽  
Large Scale ◽  
3D Cell Culture ◽  
3D Cell Cultures ◽  
Culture Formation ◽  
Large Scale Integration ◽  
3D Printed ◽  
On Chip ◽  
Scale Integration

For integration of 3D cell cultures on microfluidic large-scale integration chips, we upscaled pneumatic membrane valves using 3D-printed replica molds. Unit cell operations for 3D cell culture formation, culture, retrieval, and fusion are designed.

scholarly journals Timing Optimization During the Physical Synthesis of Cell-Based VLSI Circuits

2017 ◽  
Author(s):  
Vinícius Dos Santos Livramento ◽  
José Luís Güntzel
Keyword(s):  
Integrated Circuits ◽  
Large Scale ◽  
Cmos Technology ◽  
Vlsi Circuits ◽  
Consumer Electronics ◽  
Clock Frequency ◽  
Wide Range ◽  
Large Scale Integration ◽  
On Chip ◽  
Scale Integration

The evolution of CMOS technology made possible integrated circuits with billions of transistors assembled into a single silicon chip, giving rise to the jargon Very-Large-Scale Integration (VLSI). VLSI circuits span a wide range class of applications, including Application Specific Circuits and Systems-On-Chip. The latter are responsible for fueling the consumer electronics market, especially in the segment of smartphones and tablets, which are responsible for pushing hardware performance requirements every new generation. The required clock frequency affects the performance of a VLSI circuit and induces timing constraints that must be properly handled by synthesis tools. This thesis focuses on techniques for timing closure of cellbased VLSI circuits, i.e. techniques able to iteratively reduce the number of timing violations until the synthesis of the synchronous digital system reaches the specified target frequency.

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