Hermetic wafer level packaging of MEMS components using through silicon via and wafer to wafer bonding technologies

2013 ◽  
Author(s):  
K. Zoschke ◽  
C.-A. Manier ◽  
M. Wilke ◽  
N. Jurgensen ◽  
H. Oppermann ◽  
...  
Keyword(s):  
Wafer Bonding ◽  
Wafer Level ◽  
Through Silicon Via ◽  
Wafer Level Packaging

Through Silicon Via Technology: Cost effective Cu-TSV Interconnects by EMC3D and Technical Challenges with Cu-TSV

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000425-000445
Author(s):  
Paul Siblerud ◽  
Rozalia Beica ◽  
Bioh Kim ◽  
Erik Young
Keyword(s):  
Low Cost ◽  
Cost Effective ◽  
High Yield ◽  
Integrated Process ◽  
Wafer Level ◽  
Through Silicon Via ◽  
Wafer Level Packaging ◽  
Current State ◽  
Future Technologies ◽  
Ic Technology

The development of IC technology is driven by the need to increase performance and functionality while reducing size, power and cost. The continuous pressure to meet those requirements has created innovative, small, cost-effective 3-D packaging technologies. 3-D packaging can offer significant advantages in performance, functionality and form factor for future technologies. Breakthrough in wafer level packaging using through silicon via technology has proven to be technologically beneficial. Integration of several key and challenging process steps with a high yield and low cost is key to the general adoption of the technology. This paper will outline the breakthroughs in cost associated with an iTSV or Via-Mid structure in a integrated process flow. Key process technologies enabling 3-D chip:Via formationInsulator, barrier and seed depositionCopper filling (plating),CMPWafer thinningDie to Wafer/chip alignment, bonding and dicing This presentation will investigate these techniques that require interdisciplinary coordination and integration that previously have not been practiced. We will review the current state of 3-D interconnects and the of a cost effective Via-first TSV integrated process.

Metal Wafer Bonding for MEMS Applications

2008 ◽  
Vol 1139 ◽  
Author(s):  
Viorel Dragoi ◽  
Gerald Mittendorfer ◽  
Franz Murauer ◽  
Erkan Cakmak ◽  
Eric Pabo
Keyword(s):  
Intermetallic Compound ◽  
Eutectic Alloy ◽  
Wafer Bonding ◽  
Alloy Layer ◽  
Manufacturing Processes ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Metal Diffusion ◽  
Metal Layers ◽  
Different Levels

AbstractMetal layers can be used as bonding layers at wafer-level in MEMS manufacturing processes for device assembly as well as just for electrical integration of different levels. One has to distinguish between two main types of processes: metal diffusion bonding and bonding with formation of an interface eutectic alloy layer or an intermetallic compound. The different process principles determine also the applications area for each. From electrical interconnections to wafer-level packaging (with emphasis on vacuum packaging) metal wafer bonding is a very important technology in MEMS manufacturing processes.

Patterned Permanent Bonding of Benzocyclobutene Based Dielectric Materials for Advanced Wafer Level Packaging

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 000886-000912
Author(s):  
Jong-Uk Kim ◽  
Anupam Choubey ◽  
Rosemary Bell ◽  
Hua Dong ◽  
Michael Gallagher ◽  
...  
Keyword(s):  
Wafer Bonding ◽  
Dielectric Materials ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Integration Schemes ◽  
Device Reliability ◽  
Package Size ◽  
Microelectronics Industry ◽  
Improve Device ◽  
Joining Process

The microelectronics industry is being continually challenged to decrease package size, lower power consumption and improve device performance for the mobile communication and server markets. In order to keep pace with these requirements, device manufacturers and assembly companies are focused on developing 3D-TSV integration schemes that will require stacking of 50 um thinned wafers with gaps of 15 microns or less. While conventional underfill approaches have been demonstrated for chip to chip and chip to wafer schemes, new materials and processes are required for wafer to wafer bonding given the target bondline and wafer handling issues. Photopatternable, low temperature curable dielectrics offer a potential solution to solve the issues by eliminating the need for flow and material entrapment during the joining process. This should result in a simplified bonding process that enables wafer to wafer bonding with improved device reliability. In this work, we will focus on validating the critical steps including patterning and bonding that are required to demonstrate the utility of this process using an aqueous developable benzocyclobutene based photodielectric material.

Design and Fabrication of WLP Compatible Miniaturized Pressure Sensor System with Through Silicon Via (TSV) Interconnects

2011 ◽  
Vol 2011 (1) ◽  
pp. 000033-000043 ◽  
Author(s):  
Tao WANG ◽  
Jian CAI ◽  
Qian WANG ◽  
Hao ZHANG ◽  
Zheyao WANG
Keyword(s):  
Pressure Sensor ◽  
Flip Chip ◽  
Electrical Signal ◽  
Sensor System ◽  
Wafer Level ◽  
Through Silicon Via ◽  
Bonding Structure ◽  
Wafer Level Packaging ◽  
Piezoresistive Pressure Sensor ◽  
Processing Circuit

In this paper, a Wafer Level Packaging (WLP) compatible pressure sensor system enabled with Through Silicon Via (TSV) and Au-Sn inter-chip micro-bump bonding is designed and fabricated in lab, in which TSV transmits electrical signal from piezoresistive circuit to processing circuit vertically. The pressure sensor system includes TSV integrated piezoresistive pressure sensor chip and Read-Out Integrated Chip (ROIC) in which TSV also incorporated. Two CMOS compatible fabrication process flows for pressure sensor system are demonstrated. And, flip chip bonding structure of TSV integrated pressure sensor with a ROIC are realized using one of these two process flows. Inter-chip interconnects enabled with TSV and micro-bump bonding is obtained.

Wafer Bonding Processes for the Manufacture of Microsystems

2008 ◽  
Author(s):  
Tony Rogers ◽  
Nick Aitken
Keyword(s):  
Bond Strength ◽  
Wafer Bonding ◽  
High Efficiency ◽  
Glass Frit ◽  
Acoustic Microscopy ◽  
Anodic Bonding ◽  
High Yield ◽  
Mems Devices ◽  
Wafer Level ◽  
Wafer Level Packaging

Wafer bonding is a widely used step in the manufacture of Microsystems, and serves several purposes: • Structural component of the MEMS device. • First level packaging. • Encapsulation of vacuum or controlled gas. In addition the technology is becoming more widely used in IC fabrication for wafer level packaging (WLP) and 3D integration. It is also widely used for the fabrication of micro fluidic structures and in the manufacture of high efficiency LED’s. Depending on the application, temperature constraints, material compatibility etc. different wafer bonding processes are available, each with their own benefits and drawbacks. This paper describes various wafer bonding processes that are applicable, not only to silicon, but other materials such as glass and quartz that are commonly used in MEMS devices. The process of selecting the most appropriate bonding process for the particular application is presented along with examples of anodic, glass frit, eutectic, direct, adhesive and thermo-compression bonding. The examples include appropriate metrology for bond strength and quality. The paper also addresses the benefits of being able to treat the wafer surfaces in-situ prior to bonding in order to improve yield and bond strength, and also discusses equipment requirements for achieving high yield wafer bonding, along with high precision alignment accuracy, good force and temperature uniformity, high wafer throughput, etc. Some common problems that can affect yield are identified and discussed. These include local temperature variations, that can occur with anodic bonding, and how to eliminate them; how to cope with materials of different thermal expansion coefficient; how best to deal with out-gassing and achieve vacuum encapsulation; and procedures for multi-stacking wafers of differing thicknesses. The presentation includes infra-red and scanning acoustic microscopy images of various bond types, plus some examples of what can go wrong if the correct manufacturing protocol is not maintained.

Through-Silicon-Via (TSV) for silicon package: ″via-bridge″ approach

2012 ◽  
Vol 2012 (1) ◽  
pp. 000233-000238 ◽  
Author(s):  
Y. Lamy ◽  
S. Joblot ◽  
C. Ferrandon ◽  
J.F. Carpentier ◽  
G. Simon
Keyword(s):  
High Temperature ◽  
Low Cost ◽  
Wafer Level ◽  
Electrical Measurements ◽  
Through Silicon Via ◽  
Wafer Level Packaging ◽  
High Temperature Process ◽  
Bridge Approach ◽  
Different Diameters ◽  
Dry Film

We present in this paper an alternative Through-Silicon-Via approach that can meet the new requirements of Si package. In this wafer level packaging scheme, a thick silicon interposer (200 to 300μm) is directly reported on a PCB. In 200mm Si wafers, we made a two steps TSV composed of two vias: a top via and a bottom via. The top via is etched with DRIE (diameter 60μm, depth 180 μm, Aspect Ratio = AR>3), and insulated with high temperature dielectric. After dry film lithography, the TSV is partially plated with Cu limiting the process costs (short plating time, no CMP) and the stress inside the TSV. After temporary carrier bonding, the wafer is backgrinded so that 15μm remains below the bottom of the main TSV. Backside lithography and DRIE process create the bottom via (four different diameters: 10-20-30 and 40μm) to contact main TSV. A final backside Cu plating of the opening completed the process. This via bridges the gap between via-last (AR<2) and via-middle (AR>7) and combines high temperature process from via-middle and low-cost processing from via-last. The mechanical simulations show that this ″TSV bridge″ has reduced residual stresses inside the TSV. Our electrical measurements exhibit an average single TSV resistance below 10mOhms with excellent yield (∼95% on Kelvin and 82 TSV chains), and low contact resistances (4.7×10−9 Ω.cm2) extrapolated on 4 different contact diameters. This 200μm deep TSV seems therefore very promising for low-cost thick interposer applications.

Sign in / Sign up

Export Citation Format

Share Document