Scalable Through Silicon Via with polymer deep trench isolation for 3D wafer level packaging

2009 ◽  
Author(s):  
Deniz S. Tezcan ◽  
Fabrice Duval ◽  
Harold Philipsen ◽  
Ole Luhn ◽  
Philippe Soussan ◽  
...  
Keyword(s):  
Wafer Level ◽  
Through Silicon Via ◽  
Deep Trench ◽  
Wafer Level Packaging ◽  
Trench Isolation

Through Silicon Via Technology: Cost effective Cu-TSV Interconnects by EMC3D and Technical Challenges with Cu-TSV

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000425-000445
Author(s):  
Paul Siblerud ◽  
Rozalia Beica ◽  
Bioh Kim ◽  
Erik Young
Keyword(s):  
Low Cost ◽  
Cost Effective ◽  
High Yield ◽  
Integrated Process ◽  
Wafer Level ◽  
Through Silicon Via ◽  
Wafer Level Packaging ◽  
Current State ◽  
Future Technologies ◽  
Ic Technology

The development of IC technology is driven by the need to increase performance and functionality while reducing size, power and cost. The continuous pressure to meet those requirements has created innovative, small, cost-effective 3-D packaging technologies. 3-D packaging can offer significant advantages in performance, functionality and form factor for future technologies. Breakthrough in wafer level packaging using through silicon via technology has proven to be technologically beneficial. Integration of several key and challenging process steps with a high yield and low cost is key to the general adoption of the technology. This paper will outline the breakthroughs in cost associated with an iTSV or Via-Mid structure in a integrated process flow. Key process technologies enabling 3-D chip:Via formationInsulator, barrier and seed depositionCopper filling (plating),CMPWafer thinningDie to Wafer/chip alignment, bonding and dicing This presentation will investigate these techniques that require interdisciplinary coordination and integration that previously have not been practiced. We will review the current state of 3-D interconnects and the of a cost effective Via-first TSV integrated process.

Design and Fabrication of WLP Compatible Miniaturized Pressure Sensor System with Through Silicon Via (TSV) Interconnects

2011 ◽  
Vol 2011 (1) ◽  
pp. 000033-000043 ◽  
Author(s):  
Tao WANG ◽  
Jian CAI ◽  
Qian WANG ◽  
Hao ZHANG ◽  
Zheyao WANG
Keyword(s):  
Pressure Sensor ◽  
Flip Chip ◽  
Electrical Signal ◽  
Sensor System ◽  
Wafer Level ◽  
Through Silicon Via ◽  
Bonding Structure ◽  
Wafer Level Packaging ◽  
Piezoresistive Pressure Sensor ◽  
Processing Circuit

In this paper, a Wafer Level Packaging (WLP) compatible pressure sensor system enabled with Through Silicon Via (TSV) and Au-Sn inter-chip micro-bump bonding is designed and fabricated in lab, in which TSV transmits electrical signal from piezoresistive circuit to processing circuit vertically. The pressure sensor system includes TSV integrated piezoresistive pressure sensor chip and Read-Out Integrated Chip (ROIC) in which TSV also incorporated. Two CMOS compatible fabrication process flows for pressure sensor system are demonstrated. And, flip chip bonding structure of TSV integrated pressure sensor with a ROIC are realized using one of these two process flows. Inter-chip interconnects enabled with TSV and micro-bump bonding is obtained.

Through-Silicon-Via (TSV) for silicon package: ″via-bridge″ approach

2012 ◽  
Vol 2012 (1) ◽  
pp. 000233-000238 ◽  
Author(s):  
Y. Lamy ◽  
S. Joblot ◽  
C. Ferrandon ◽  
J.F. Carpentier ◽  
G. Simon
Keyword(s):  
High Temperature ◽  
Low Cost ◽  
Wafer Level ◽  
Electrical Measurements ◽  
Through Silicon Via ◽  
Wafer Level Packaging ◽  
High Temperature Process ◽  
Bridge Approach ◽  
Different Diameters ◽  
Dry Film

We present in this paper an alternative Through-Silicon-Via approach that can meet the new requirements of Si package. In this wafer level packaging scheme, a thick silicon interposer (200 to 300μm) is directly reported on a PCB. In 200mm Si wafers, we made a two steps TSV composed of two vias: a top via and a bottom via. The top via is etched with DRIE (diameter 60μm, depth 180 μm, Aspect Ratio = AR>3), and insulated with high temperature dielectric. After dry film lithography, the TSV is partially plated with Cu limiting the process costs (short plating time, no CMP) and the stress inside the TSV. After temporary carrier bonding, the wafer is backgrinded so that 15μm remains below the bottom of the main TSV. Backside lithography and DRIE process create the bottom via (four different diameters: 10-20-30 and 40μm) to contact main TSV. A final backside Cu plating of the opening completed the process. This via bridges the gap between via-last (AR<2) and via-middle (AR>7) and combines high temperature process from via-middle and low-cost processing from via-last. The mechanical simulations show that this ″TSV bridge″ has reduced residual stresses inside the TSV. Our electrical measurements exhibit an average single TSV resistance below 10mOhms with excellent yield (∼95% on Kelvin and 82 TSV chains), and low contact resistances (4.7×10−9 Ω.cm2) extrapolated on 4 different contact diameters. This 200μm deep TSV seems therefore very promising for low-cost thick interposer applications.

Tapered Through-Silicon-Via Interconnects for Wafer-Level Packaging of Sensor Devices

2010 ◽  
Vol 33 (3) ◽  
pp. 713-721 ◽  
Author(s):  
Jüergen Leib ◽  
Florian Bieck ◽  
Ulli Hansen ◽  
Kok-Kheong Looi ◽  
Ha-Duong Ngo ◽  
...  
Keyword(s):  
Wafer Level ◽  
Through Silicon Via ◽  
Wafer Level Packaging ◽  
Sensor Devices

Antenna-in-Package Design Based on Wafer-Level Packaging With Through Silicon Via Technology

2013 ◽  
Vol 3 (9) ◽  
pp. 1498-1505 ◽  
Author(s):  
Cheng Jin ◽  
Vasarla Nagendra Sekhar ◽  
Xiaoyue Bao ◽  
Bangtao Chen ◽  
Boyu Zheng ◽  
...  
Keyword(s):  
Wafer Level ◽  
Through Silicon Via ◽  
Package Design ◽  
Wafer Level Packaging

Formation of defects in implanted hipox-structures

1992 ◽  
Vol 50 (2) ◽  
pp. 1406-1407
Author(s):  
Peter Pegler ◽  
N. David Theodore ◽  
Ming Pan
Keyword(s):  
High Pressure ◽  
Cross Section ◽  
Semiconductor Devices ◽  
Silicon Substrates ◽  
Processing Conditions ◽  
Pressure Oxidation ◽  
Deep Trench ◽  
Local Oxidation ◽  
Trench Isolation ◽  
And Behavior

High-pressure oxidation of silicon (HIPOX) is one of various techniques used for electrical-isolation of semiconductor-devices on silicon substrates. Other techniques have included local-oxidation of silicon (LOCOS), poly-buffered LOCOS, deep-trench isolation and separation of silicon by implanted oxygen (SIMOX). Reliable use of HIPOX for device-isolation requires an understanding of the behavior of the materials and structures being used and their interactions under different processing conditions. The effect of HIPOX-related stresses in the structures is of interest because structuraldefects, if formed, could electrically degrade devices.This investigation was performed to study the origin and behavior of defects in recessed HIPOX (RHIPOX) structures. The structures were exposed to a boron implant. Samples consisted of (i) RHlPOX'ed strip exposed to a boron implant, (ii) recessed strip prior to HIPOX, but exposed to a boron implant, (iii) test-pad prior to HIPOX, (iv) HIPOX'ed region away from R-HIPOX edge. Cross-section TEM specimens were prepared in the <110> substrate-geometry.

MEMS Wafer-level Packaging Technology Using LTCC Wafer

2012 ◽  
Vol 132 (8) ◽  
pp. 246-253 ◽  
Author(s):  
Mamoru Mohri ◽  
Masayoshi Esashi ◽  
Shuji Tanaka
Keyword(s):  
Wafer Level ◽  
Packaging Technology ◽  
Wafer Level Packaging
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