Fabrication of High Aspect Ratio 35 /spl mu/m Pitch Interconnects for Next Generation 3-D Wafer-Level Packaging by Through-Wafer Copper Electroplating

2006 ◽  
Author(s):  
P. Dixit ◽  
Jianmin Miao
Keyword(s):  
Aspect Ratio ◽  
High Aspect Ratio ◽  
Next Generation ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Copper Electroplating

3D system integration on 300 mm wafer level: High-aspect-ratio TSVs with ruthenium seed layer by thermal ALD and subsequent copper electroplating

2019 ◽  
Vol 205 ◽  
pp. 20-25 ◽  
Author(s):  
Sebastian Killge ◽  
Irene Bartusseck ◽  
Marcel Junige ◽  
Volker Neumann ◽  
Johanna Reif ◽  
...  
Keyword(s):  
Aspect Ratio ◽  
High Aspect Ratio ◽  
System Integration ◽  
Seed Layer ◽  
Wafer Level ◽  
Copper Electroplating

Wafer-Scale, Highly-Ordered Silicon Nanowires Produced by Step-and-Flash Imprint Lithography and Metal-Assisted Chemical Etching

2012 ◽  
Vol 1512 ◽  
Author(s):  
Jian-Wei Ho ◽  
Qixun Wee ◽  
Jarrett Dumond ◽  
Li Zhang ◽  
Keyan Zang ◽  
...  
Keyword(s):  
Aspect Ratio ◽  
Cross Sections ◽  
Silicon Nanowires ◽  
High Aspect Ratio ◽  
Chemical Etching ◽  
Semiconductor Device ◽  
Imprint Lithography ◽  
Wafer Level ◽  
Conventional Photolithography ◽  
Metal Assisted Chemical Etching

ABSTRACTA combinatory approach of Step-and-Flash Imprint Lithography (SFIL) and Metal-Assisted Chemical Etching (MacEtch) was used to generate near perfectly-ordered, high aspect ratio silicon nanowires (SiNWs) on 4" silicon wafers. The ordering and shapes of SiNWs depends only on the SFIL nanoimprinting mould used, thereby enabling arbitary SiNW patterns not possible with nanosphere and interference lithography (IL) to be generated. Very densely packed SiNWs with periodicity finer than that permitted by conventional photolithography can be produced. The height of SiNWs is, in turn, controlled by the etching duration. However, it was found that very high aspect ratio SiNWs tend to be bent during processing. Hexagonal arrays of SiNW with circular and hexagonal cross-sections of dimensions 200nm and less were produced using pillar and pore patterned SFIL moulds. In summary, this approach allows highlyordered SiNWs to be fabricated on a wafer-level basis suitable for semiconductor device manufacturing.

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