Integrated electrical, optical, and thermal high density and compliant wafer-level chip I/O interconnections for gigascale integration

2004 ◽  
Author(s):  
M.S. Bakir ◽  
J.D. Meindl
Keyword(s):  
High Density ◽  
Wafer Level ◽  
Gigascale Integration

Ultra-High-Density Interconnect Enabled by Hybrid Bonding for Heterogeneous Integration: Interfacial Characteristics

2021 ◽  
Author(s):  
Mei-Chien Lu
Keyword(s):  
Performance Metrics ◽  
High Volume ◽  
Image Sensor ◽  
Structure Design ◽  
High Density ◽  
Heterogeneous Integration ◽  
Wafer Level ◽  
Bonding Area ◽  
The Impact ◽  
Interfacial Characteristics

Abstract Hybrid bonding has been explored for more than a decade and implemented recently in high volume production at wafer-to-wafer level for image sensor applications to enable high performance chip-stacking architectures with ultra-high-density chip-to-chip interconnect. The feasibility of sub-micron hybrid bond pitch leading to ultra-high-density chip-to-chip interconnect has been demonstrated due to the elimination of solder bridging issues from microbump method. Hybrid bonding has also been actively considered for logic and memory chip-stacking, chiplets, and heterogeneous integration in general but encountering additional challenges for bonding at die-to-wafer or die-to-die level. Overlay precision, throughput, wafer dicing are among the main causes. Widening the process margin against overlay error by designing innovative hybrid bonding pad structure is highly desirable. This work proposes a method to evaluate these hybrid bonding pad structure designs and to assess the potential performance metrics by analyzing interfacial characteristics at design phase. The bonding areas and ratios of copper-copper, copper-dielectric, and dielectric-dielectric are the proposed key parameters. The correlation between bonding area ratios and overlay errors can provide insights on the sensitivity to process margins. Nonetheless, the impact of copper recess or protrusion associated with bonding area ratios are also highlighted. The proposed method is demonstrated by examining and analyzing the hybrid bonding pad structure design concepts from a few cases reported in literatures as examples. Concerns are identified for elaboration in future designs and optimizations.

Development of High Density RDL Technologies for Panel Level Processing

2019 ◽  
Vol 2019 (DPC) ◽  
pp. 000284-000313
Author(s):  
Lars Böttcher ◽  
S. Karaszkiewicz ◽  
F. Schein ◽  
R. Kahle ◽  
A. Ostmann
Keyword(s):  
Coefficient Of Thermal Expansion ◽  
High Density ◽  
Organic Films ◽  
High Yield ◽  
Wafer Level ◽  
Final Size ◽  
Process Yield ◽  
Cu Pillar ◽  
Thin Organic Films ◽  
Advanced Packaging

Advanced packaging technologies like wafer-level fan-out and 3D System-in-Packages (SIPs) are rapidly penetrating the market of electronic components. A recent trend to reduce cost is the extension of processes to large manufacturing formats, called Panel Level Packaging (PLP). In a consortium of German partners from industry and research advanced technologies for PLP are developed. The project aims for an integrated process flow for SIPs with chips embedded into an organic laminate matrix. At first dies with Cu pillar structures are placed into openings of a laminate frame layer with very low coefficient of thermal expansion (CTE). They are embedded by vacuum lamination of thin organic films, filling the very small gap down to 15 μm between chips and frame. The frame provides alignment marks for a local registration of following processes. The ridged frame limits die shift during embedding and gives a remarkable handling robustness. Developments are initially performed on a 305×256mm2 panel format, aiming for a final size of 610×615 mm2. On the top side of embedded chips, a 20μm dielectric film is applied. The goal is to avoid additional via formation and to realize a direct connection between the Cu pillar of the die and the RDL The RDL formation is based on semi-additive processing. Therefore a Ti or TiW barrier and Cu seed layer is sputtered. Subsequently a 7μm photoresist is applied and exposed by a newly developed Direct Imaging (DI) system. Lines and spaces of 4μm were achieved with high yield. In the following, Cu is simultaneously electroplated for the via contacts and interconnects traces. Finally, the photo resist is stripped and the TiW barrier and Cu seed layers are etched. The goal of the development is to provide a technology for a high-density RDL formation on large panel sizes. The paper will discuss the new developments in detail, e.g. the influence of most significant process parameters, like lithographical resolution, minimum via diameter and the placement and alignment accuracy on overall process yield.

Cost-Effective Precision 3D Glass Microfabrication for Advanced Packaging Applications

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 000791-000810
Author(s):  
Jeb Flemming ◽  
Roger Cook ◽  
Kevin Dunn ◽  
James Gouker
Keyword(s):  
Cost Effective ◽  
High Density ◽  
Consumer Electronics ◽  
Liquid Crystal Polymers ◽  
Portable Devices ◽  
Signal Loss ◽  
Wafer Level ◽  
Advanced Packaging ◽  
And Performance ◽  
Optical Waveguiding

Today's packaging has become the limiting element in system cost and performance for IC development. Assembly and packaging technologies have become primary differentiators for manufactures of consumer electronics and the main enabler of small IC product development. Traditional packaging approaches to address the needs in these “High Density Portable” devices, including FR4, liquid crystal polymers, and Low Temperature Co-Fire Ceramics, are running into fundamental limits in packaging layer thinness, high density interconnects (HDI) size and density, and do not present solutions to in-package thermal management, and optical waveguiding. In this talk, 3D Glass Solutions will present on our efforts to create advanced microelectronic packing solutions using our APEX™ Glass ceramic which offers a single material capable of being simultaneously used for ultra-HDI through glass vias (TGVs), optical waveguiding, and in-package microfluidic cooling. In this talk we will discuss our latest results in wafer-level microfabrication of packaging solutions. We will present on our efforts for creating copper filled vias, surface metallization, and passivation. Furthermore, we will present our efforts in exploring this material to produce (1) ultra-HDI glass interposers, with TGVs as small as 12 microns, with 14 micron center –to-center, (2) advanced RF packages with unique surface architectures designed to minimize signal loss, and (3) creating wave guiding structures in HDI packages.

Sea of leads (SoL) ultrahigh density wafer-level chip input/output interconnections for gigascale integration (GSI)

2003 ◽  
Vol 50 (10) ◽  
pp. 2039-2048 ◽  
Author(s):  
M.S. Bakir ◽  
H.A. Reed ◽  
H.D. Thacker ◽  
C.S. Patel ◽  
P.A. Kohl ◽  
...  
Keyword(s):  
Input Output ◽  
Wafer Level ◽  
Gigascale Integration ◽  
Ultrahigh Density

High-density interconnect board design for wafer-level packaging

2011 ◽  
Vol 47 (20) ◽  
pp. 1137 ◽  
Author(s):  
B. Wu ◽  
B. Brown ◽  
E. Warner
Keyword(s):  
High Density ◽  
Wafer Level ◽  
Wafer Level Packaging
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