Characterization of wafer level package for mobile phone application

2002 ◽  
Author(s):  
Ji-Yon Kim ◽  
I.S. Kang ◽  
M.G. Park ◽  
J.H. Kim ◽  
S.J. Cho ◽  
...  
Keyword(s):  
Mobile Phone ◽  
Wafer Level ◽  
Mobile Phone Application ◽  
Wafer Level Package

Thermal modeling and characterization of the embedded micro wafer level package (EMWLP) at the package- and system-level

2009 ◽  
Author(s):  
Yen Yi Germaine Hoe ◽  
Tang Gongyue ◽  
Gaurav Sharma ◽  
Damaragunath Pinjala ◽  
Vempati Srinivasa Rao ◽  
...  
Keyword(s):  
Thermal Modeling ◽  
System Level ◽  
Wafer Level ◽  
Wafer Level Package

Mobile Phone Application for Supporting Persons with Higher Brain Dysfunctions

2010 ◽  
Vol 130 (3) ◽  
pp. 394-400
Author(s):  
Tsuyoshi Nakayama ◽  
Yuka Miyaji ◽  
Seishi Kato ◽  
Nobuhisa Sakurada ◽  
Noriyuki Ueda ◽  
...  
Keyword(s):  
Mobile Phone ◽  
Mobile Phone Application

Characterization of Unfilled Tungsten Plugs on a 0.35μm CMOS Multilevel Metallization Process

1996 ◽  
Author(s):  
H. Sur ◽  
S. Bothra ◽  
Y. Strunk ◽  
J. Hahn
Keyword(s):  
Process Development ◽  
Process Integration ◽  
Wafer Level ◽  
Electrical Failure ◽  
Analysis Techniques ◽  
Integration Approach ◽  
Intermetal Dielectric ◽  
Metallization Process ◽  
Section Analysis

Abstract An investigation into metallization/interconnect failures during the process development phase of an advanced 0.35μm CMOS ASIC process is presented. The corresponding electrical failure signature was electrical shorting on SRAM test arrays and subsequently functional/Iddq failures on product-like test vehicles. Advanced wafer-level failure analysis techniques and equipment were used to isolate and identify the leakage source as shorting of metal lines due to tungsten (W) residue which was originating from unfilled vias. Further cross-section analysis revealed that the failing vias were all exposed to the intermetal dielectric spin-on glass (SOG) material used for filling the narrow spaces between metal lines. The outgassing of the SOG in the exposed regions of the via prior to and during the tungsten plug deposition is believed to be the cause of the unfilled vias. This analysis facilitated further process development in eliminating the failure mechanism and since then no failures of this nature have been observed. The process integration approach used to eliminate the failure is discussed.

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