Wafer level warpage characterization of 3D interconnect processing wafers

2012 ◽  
Author(s):  
Po-Yi Chang ◽  
Yi-Sha Ku
Keyword(s):  
Wafer Level

Characterization of Unfilled Tungsten Plugs on a 0.35μm CMOS Multilevel Metallization Process

1996 ◽  
Author(s):  
H. Sur ◽  
S. Bothra ◽  
Y. Strunk ◽  
J. Hahn
Keyword(s):  
Process Development ◽  
Process Integration ◽  
Wafer Level ◽  
Electrical Failure ◽  
Analysis Techniques ◽  
Integration Approach ◽  
Intermetal Dielectric ◽  
Metallization Process ◽  
Section Analysis

Abstract An investigation into metallization/interconnect failures during the process development phase of an advanced 0.35μm CMOS ASIC process is presented. The corresponding electrical failure signature was electrical shorting on SRAM test arrays and subsequently functional/Iddq failures on product-like test vehicles. Advanced wafer-level failure analysis techniques and equipment were used to isolate and identify the leakage source as shorting of metal lines due to tungsten (W) residue which was originating from unfilled vias. Further cross-section analysis revealed that the failing vias were all exposed to the intermetal dielectric spin-on glass (SOG) material used for filling the narrow spaces between metal lines. The outgassing of the SOG in the exposed regions of the via prior to and during the tungsten plug deposition is believed to be the cause of the unfilled vias. This analysis facilitated further process development in eliminating the failure mechanism and since then no failures of this nature have been observed. The process integration approach used to eliminate the failure is discussed.

scholarly journals Characterization of Wafer-Level Thermocompression Bonds

2004 ◽  
Vol 13 (6) ◽  
pp. 963-971 ◽  
Author(s):  
C.H. Tsau ◽  
S.M. Spearing ◽  
M.A. Schmidt
Keyword(s):  
Wafer Level

Characterization of Wafer-Level Au-In-Bonded Samples at Elevated Temperatures

2015 ◽  
Vol 46 (6) ◽  
pp. 2637-2645 ◽  
Author(s):  
Thi-Thuy Luu ◽  
Nils Hoivik ◽  
Kaiying Wang ◽  
Knut E. Aasmundtveit ◽  
Astrid-Sofie B. Vardøy
Keyword(s):  
Elevated Temperatures ◽  
Wafer Level

Design and characterization of a biocompatible packaging concept for implantable electronic devices

2011 ◽  
Vol 2011 (1) ◽  
pp. 000152-000160 ◽  
Author(s):  
Maaike Op de Beeck ◽  
Karen Qian ◽  
Paolo Fiorini ◽  
Karl Malachowski ◽  
Chris Van Hoof
Keyword(s):  
Diffusion Barrier ◽  
Barrier Properties ◽  
The Body ◽  
Second Phase ◽  
Electronic Systems ◽  
Wafer Level ◽  
Packaging Process ◽  
Directional Diffusion ◽  
Chip Sealing

A biocompatible packaging process for implantable electronic systems is described, combining biocompatibility and hermeticity with extreme miniaturization. In a first phase of the total packaging sequence, all chips are encapsulated in order to realize a bi-directional diffusion barrier preventing body fluids to leach into the package causing corrosion, and preventing IC materials such as Cu to diffuse into the body, causing various adverse effects. For cost effectiveness, this hermetic chip sealing is performed as post-processing at wafer level, using modifications of standard clean room (CR) fabrication techniques. Well known conductive and insulating CR materials are investigated with respect to their biocompatibility, diffusion barrier properties and sensitivity to corrosion. In a second phase of the packaging process, all chips of the final device should be electrically connected, applying a biocompatible metallization scheme using eg. gold or platinum. For electrodes being in direct contact with the tissue after implantation, IrOx metallization is proposed. Device assembly is the final packaging step, during which all system components such as electronics, passives, a battery,… will be interconnected. To provide sufficient mechanical support, all these components are embedded using a biocompatible elastomer such as PDMS.

Design and electrical characterization of wafer-level micro-package for GaAs-based RFMEMS switches

2013 ◽  
Vol 59 (3) ◽  
pp. 201 ◽  
Author(s):  
Sandeep Chaturvedi ◽  
GSai Saravanan ◽  
MahadevaK Bhat ◽  
R Muralidharan ◽  
ShibanK Koul ◽  
...  
Keyword(s):  
Electrical Characterization ◽  
Wafer Level

Reliability and Characterization of Micro-Packages in a Wafer Level Au-Si Eutectic Vacuum Bonding Process

2005 ◽  
Author(s):  
Jay S. Mitchell ◽  
Gholamhassan R. Lahiji ◽  
Khalil Najafi
Keyword(s):  
High Sensitivity ◽  
Pressure Change ◽  
Bonding Process ◽  
Wafer Level ◽  
Eutectic Solder ◽  
Packaging Process ◽  
Primary Mechanism ◽  
Airtight Seal ◽  
Over Time

A Au-Si eutectic vacuum packaging process was evaluated using high sensitivity poly-Si Pirani vacuum sensors. Encapsulation of devices was achieved by bonding a silicon cap wafer to a device wafer using a Au-Si eutectic solder at above 390°C in a vacuum bonder. The Au-Si eutectic solder encircled the devices, providing an airtight seal. The Pirani gauges were encapsulated and tested over a period of several months in order to determine base pressures and leak/outgassing rates of the micro-cavities. Packaged devices without getters showed initial pressures from 2 to 12 Torr with initial leak/outgassing rates of −0.073 to 80 Torr/year. Using getters, pressures as low as 5 mTorr have been achieved with leak/outgassing rates of <10 mTorr/year. Trends in pressure over time seem to indicate outgassing (desorption of atoms from inside of the microcavity) as the primary mechanism for pressure change over time.

Sign in / Sign up

Export Citation Format

Share Document