Design and electrical characterization of a novel wafer level package for RF MEMS applications

Author(s):  
N.D. Rotaru ◽  
C.S. Premachandran ◽  
M.K. Iyer
Author(s):  
Renu Sharma ◽  
Isha Yadav ◽  
Anupriya Katiyar ◽  
Milap Singh ◽  
Shaveta ◽  
...  

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001937-001962
Author(s):  
Kai Liu ◽  
YongTaek Lee ◽  
HyunTai Kim ◽  
MaPhooPwint Hlaing ◽  
Susan Park ◽  
...  

In this paper, a 2-layer eWLB (embedded Wafer-Level BGA) is studied and its performance is compared with an equivalent 4-layer laminate package. Since eWLB package is processed by using lithographical method, design rules on width (W) and spacing (S) are much finer (usually 2–3 times finer) than those for laminate package. In other words, signal traces can be implemented in smaller fan-out regions. The smaller feature sizes for signal traces would end up with more metal loss per unit length. But as the signal traces can be implemented in smaller fan-out regions, overall trace-routing may be shorter, and equivalent insertion-loss may be achieved. In eWLB, the ground plane is closer to the signal traces. This actually helps to reduce cross-talk between wide I/O buses, as the electrical field is contained in a smaller region by the closer ground plane. Another key advantage from wafer-level package is a smoother metal surface, which greatly reduces the extra signal loss, due to surface-roughness effect, especially for higher-frequency and higher-speed applications. In addition, through-via structures for wafer-level package are typically 2–3 times smaller. This allows to implement power/ground planes in a more continuous way, achieving better resistance and inductance for power/ground nets. Overall electrical performance, which takes into account of all the impacts above, can be evaluated by signal-integrity analysis (E-diagram). Measurement data of a 2-layer eWLB package for a LPDDR application will be presented, which shows the comparable performance typically obtained from a 4-layer laminate package


2013 ◽  
Vol 59 (3) ◽  
pp. 201 ◽  
Author(s):  
Sandeep Chaturvedi ◽  
GSai Saravanan ◽  
MahadevaK Bhat ◽  
R Muralidharan ◽  
ShibanK Koul ◽  
...  

2008 ◽  
Vol 142 (1) ◽  
pp. 434-441 ◽  
Author(s):  
J. Iannacci ◽  
M. Bartek ◽  
J. Tian ◽  
R. Gaddi ◽  
A. Gnudi

2010 ◽  
Vol 2010 ◽  
pp. 1-5 ◽  
Author(s):  
Anna Persano ◽  
Fabio Quaranta ◽  
Adriano Cola ◽  
Antonietta Taurino ◽  
Giorgio De Angelis ◽  
...  

Shunt capacitive RF MEMS switches have been developed using III-V technology and employing (tantalum pentoxide) Ta2O5thin films as dielectric layers. In order to evaluate the potential of the Ta2O5thin films for the considered application, the compositional, structural, and electrical characterization of the deposited films has been performed, demonstrating that they are good candidates to be used as dielectric layers for the fabrication of RF MEMS switches. Specifically, Ta2O5films are found to show a leakage current density of few nA/cm2forE∼1 MV/cm and a high dielectric constant of 32. Moreover, the charging process has been investigated, finding that it follows a stretched exponential law. The fabricated switches show actuation voltages in the range 15–20 V, an insertion loss better than −0.8 dB up to 30 GHz, and an isolation of ~−40 dB at the resonant frequency which is around 25 GHz.


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