On-line error detection for finite field multipliers

2002 ◽  
Author(s):  
M. Gossel ◽  
S. Fenn ◽  
D. Taylor
Keyword(s):  
Finite Field ◽  
Error Detection ◽  
On Line

Fault Tolerant Techniques for Finite Field Multipliers

2014 ◽  
Vol 573 ◽  
pp. 209-214
Author(s):  
B. Sargunam ◽  
R. Dhanasekaran
Keyword(s):  
Finite Field ◽  
Error Detection ◽  
Fault Tolerant ◽  
High Reliability ◽  
Concurrent Error Detection ◽  
Polynomial Representation ◽  
Finite Field Multiplier ◽  
On Line ◽  
Error Detecting ◽  
Modular Redundancy

The use of finite field multipliers in the critical applications like elliptic curve cryptography needs Concurrent Error Detection (CED) and correction at architectural level to provide high reliability. This paper discusses fault tolerant technique for polynomial representation based finite field multipliers. The detection and correction are done on-line. We use a combination of Double Modular Redundancy (DMR) and Concurrent Error Detection (CED) techniques. The fault tolerant finite field multiplier is coded in VHDL and simulated using Modelsim. Further, the proposed multiplier with fault tolerant capability is synthesized and results are analyzed with respect to area occupied, input and output pin counts and delay. Our technique, when compared with existing techniques, gives better performance. We show that our concurrent error detecting multiplier over GF(2m) requires less than 200% extra hardware, whereas with the traditional fault tolerant techniques, such as Triple Modular Redundancy (TMR), overhead is more than 200%.

CRC-Based Error Detection Constructions for FLT and ITA Finite Field Inversions Over GF(2 m )

2021 ◽  
Vol 29 (5) ◽  
pp. 1033-1037
Author(s):  
Alvaro Cintas Canto ◽  
Mehran Mozaffari Kermani ◽  
Reza Azarderakhsh
Keyword(s):  
Finite Field ◽  
Error Detection
Sign in / Sign up

Export Citation Format

Share Document