scholarly journals Concurrent Error Detection in Finite-Field Arithmetic Operations Using Pipelined and Systolic Architectures

2009 ◽  
Vol 58 (11) ◽  
pp. 1553-1567 ◽  
Author(s):  
Siavash Bayat-Sarmadi ◽  
M.A. Hasan
Keyword(s):  
Finite Field ◽  
Error Detection ◽  
Concurrent Error Detection ◽  
Arithmetic Operations ◽  
Finite Field Arithmetic

Fault Tolerant Techniques for Finite Field Multipliers

2014 ◽  
Vol 573 ◽  
pp. 209-214
Author(s):  
B. Sargunam ◽  
R. Dhanasekaran
Keyword(s):  
Finite Field ◽  
Error Detection ◽  
Fault Tolerant ◽  
High Reliability ◽  
Concurrent Error Detection ◽  
Polynomial Representation ◽  
Finite Field Multiplier ◽  
On Line ◽  
Error Detecting ◽  
Modular Redundancy

The use of finite field multipliers in the critical applications like elliptic curve cryptography needs Concurrent Error Detection (CED) and correction at architectural level to provide high reliability. This paper discusses fault tolerant technique for polynomial representation based finite field multipliers. The detection and correction are done on-line. We use a combination of Double Modular Redundancy (DMR) and Concurrent Error Detection (CED) techniques. The fault tolerant finite field multiplier is coded in VHDL and simulated using Modelsim. Further, the proposed multiplier with fault tolerant capability is synthesized and results are analyzed with respect to area occupied, input and output pin counts and delay. Our technique, when compared with existing techniques, gives better performance. We show that our concurrent error detecting multiplier over GF(2m) requires less than 200% extra hardware, whereas with the traditional fault tolerant techniques, such as Triple Modular Redundancy (TMR), overhead is more than 200%.

DESIGN FLOW OF CONCURRENT ERROR DETECTION SCHEMES FOR COMBINATIONAL CIRCUITS

2018 ◽  
Vol 65 ◽  
pp. 92-98
Author(s):  
A. L. Stempkovskiy ◽  
◽  
D. V. Telpukhov ◽  
A. I. Demeneva ◽  
T. D. Zhukova ◽  
...  
Keyword(s):  
Error Detection ◽  
Design Flow ◽  
Concurrent Error Detection ◽  
Combinational Circuits ◽  
Detection Schemes

Concurrent error detection in VLSI interconnection networks

1983 ◽  
Vol 11 (3) ◽  
pp. 309-315 ◽  
Author(s):  
W. Kent Fuchs ◽  
Jacob A. Abraham ◽  
Kuang-Hua Huang
Keyword(s):  
Error Detection ◽  
Interconnection Networks ◽  
Concurrent Error Detection

scholarly journals (M+1)-Sequence Generators with Concurrent Error Detection

2021 ◽  
Vol 190 ◽  
pp. 361-369
Author(s):  
Mikhail Ivanov ◽  
Iliya Chugunkov ◽  
Bogdana Kliuchnikova ◽  
Evgenii Salikov
Keyword(s):  
Error Detection ◽  
Concurrent Error Detection
Sign in / Sign up

Export Citation Format

Share Document