Integration of Learning Techniques into Incremental Satisfiability for Efficient Path-Delay Fault Test Generation

Mapping Intimacies ◽

10.1109/date.2005.187 ◽

2005 ◽

Cited By ~ 11

Author(s):

K. Chandrasekar ◽

M.S. Hsiao

Keyword(s):

Test Generation ◽

Path Delay ◽

Delay Fault ◽

Learning Techniques ◽

Path Delay Fault ◽

Integration Of Learning

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Automatic path-delay fault test generation for combined resistive vias, resistive bridges, and capacitive crosstalk delay faults

19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06) ◽

10.1109/vlsid.2006.51 ◽

2006 ◽

Cited By ~ 2

Author(s):

S. Chary ◽

M.L. Bushnell

Keyword(s):

Test Generation ◽

Delay Faults ◽

Path Delay ◽

Delay Fault ◽

Path Delay Fault ◽

Resistive Bridges

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On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation

Journal of Electronic Testing ◽

10.1007/s10836-007-5020-8 ◽

2008 ◽

Vol 24 (1-3) ◽

pp. 203-222 ◽

Cited By ~ 3

Author(s):

Kyriakos Christou ◽

Maria K. Michael ◽

Spyros Tragoudas

Keyword(s):

Test Generation ◽

Critical Path ◽

Path Delay ◽

Delay Fault ◽

Critical Path Delay ◽

Path Delay Fault

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Path delay fault test generation for standard scan designs using state tuples

Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design ◽

10.1109/aspdac.2002.995026 ◽

2003 ◽

Cited By ~ 2

Author(s):

Yun Shao ◽

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Test Generation ◽

Path Delay ◽

Delay Fault ◽

Path Delay Fault

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FSimGEO: a test generation method for path delay fault test using fault simulation and genetic optimization

Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558) ◽

10.1109/asic.2001.954702 ◽

2002 ◽

Author(s):

Sun Yihe ◽

Wu Qifa

Keyword(s):

Test Generation ◽

Fault Simulation ◽

Genetic Optimization ◽

Path Delay ◽

Delay Fault ◽

Path Delay Fault

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Flags and algebra for sequential circuit VNR path delay fault test generation

Proceedings Tenth International Conference on VLSI Design ◽

10.1109/icvd.1997.567966 ◽

2002 ◽

Cited By ~ 4

Author(s):

M.K. Srinivas ◽

M.L. Bushnell ◽

V.D. Agrawal

Keyword(s):

Test Generation ◽

Path Delay ◽

Sequential Circuit ◽

Delay Fault ◽

Path Delay Fault ◽

And Algebra

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A new classification of path-delay fault testability in terms of stuck-at faults

Journal of Computer Science and Technology ◽

10.1007/bf02973460 ◽

2004 ◽

Vol 19 (6) ◽

pp. 955-964 ◽

Cited By ~ 2

Author(s):

Subhashis Majumder ◽

Bhargab B. Bhattacharya ◽

Vishwani D. Agrawal ◽

Michael L. Bushnell

Keyword(s):

Path Delay ◽

New Classification ◽

Delay Fault ◽

Path Delay Fault

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Path Delay Fault Classification

Frontiers in Electronic Testing - Delay Fault Testing for VLSI Circuits ◽

10.1007/978-1-4615-5597-1_5 ◽

1998 ◽

pp. 45-76

Author(s):

Angela Krstić ◽

Kwang-Ting Cheng

Keyword(s):

Fault Classification ◽

Path Delay ◽

Delay Fault ◽

Path Delay Fault

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Path delay fault simulation algorithms for sequential circuits

Proceedings First Asian Test Symposium (ATS `92) ◽

10.1109/ats.1992.224444 ◽

2003 ◽

Cited By ~ 13

Author(s):

T.J. Chakraborty ◽

V.D. Agrawal ◽

M.L. Bushnell

Keyword(s):

Fault Simulation ◽

Sequential Circuits ◽

Path Delay ◽

Delay Fault ◽

Path Delay Fault ◽

Simulation Algorithms

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On the design of path delay fault testable combinational circuits

[1990] Digest of Papers. Fault-Tolerant Computing: 20th International Symposium ◽

10.1109/ftcs.1990.89391 ◽

2002 ◽

Cited By ~ 78

Author(s):

A.K. Pramanick ◽

S.M. Reddy

Keyword(s):

Path Delay ◽

Combinational Circuits ◽

Delay Fault ◽

Path Delay Fault

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New advances in path delay fault testing of combinational circuits

Proceedings of IEEE VLSI Test Symposium ◽

10.1109/vtest.1994.292301 ◽

2002 ◽

Cited By ~ 3

Author(s):

X. Xie ◽

A. Albicki

Keyword(s):

Path Delay ◽

Combinational Circuits ◽

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

Path Delay Fault ◽

Path Delay Fault Testing

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