Automatic path-delay fault test generation for combined resistive vias, resistive bridges, and capacitive crosstalk delay faults

19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06) ◽

10.1109/vlsid.2006.51 ◽

2006 ◽

Cited By ~ 2

Author(s):

S. Chary ◽

M.L. Bushnell

Keyword(s):

Test Generation ◽

Delay Faults ◽

Path Delay ◽

Delay Fault ◽

Path Delay Fault ◽

Resistive Bridges

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On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation

Journal of Electronic Testing ◽

10.1007/s10836-007-5020-8 ◽

2008 ◽

Vol 24 (1-3) ◽

pp. 203-222 ◽

Cited By ~ 3

Author(s):

Kyriakos Christou ◽

Maria K. Michael ◽

Spyros Tragoudas

Keyword(s):

Test Generation ◽

Critical Path ◽

Path Delay ◽

Delay Fault ◽

Critical Path Delay ◽

Path Delay Fault

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Path delay fault test generation for standard scan designs using state tuples

Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design ◽

10.1109/aspdac.2002.995026 ◽

2003 ◽

Cited By ~ 2

Author(s):

Yun Shao ◽

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Test Generation ◽

Path Delay ◽

Delay Fault ◽

Path Delay Fault

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FSimGEO: a test generation method for path delay fault test using fault simulation and genetic optimization

Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558) ◽

10.1109/asic.2001.954702 ◽

2002 ◽

Author(s):

Sun Yihe ◽

Wu Qifa

Keyword(s):

Test Generation ◽

Fault Simulation ◽

Genetic Optimization ◽

Path Delay ◽

Delay Fault ◽

Path Delay Fault

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Flags and algebra for sequential circuit VNR path delay fault test generation

Proceedings Tenth International Conference on VLSI Design ◽

10.1109/icvd.1997.567966 ◽

2002 ◽

Cited By ~ 4

Author(s):

M.K. Srinivas ◽

M.L. Bushnell ◽

V.D. Agrawal

Keyword(s):

Test Generation ◽

Path Delay ◽

Sequential Circuit ◽

Delay Fault ◽

Path Delay Fault ◽

And Algebra

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Transition Path Delay Faults: A New Path Delay Fault Model for Small and Large Delay Defects

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2007.909796 ◽

2008 ◽

Vol 16 (1) ◽

pp. 98-107 ◽

Cited By ~ 26

Author(s):

Irith Pomeranz ◽

Sudhakar M. Reddy

Keyword(s):

Fault Model ◽

Delay Faults ◽

Path Delay ◽

Path Delay Faults ◽

Transition Path ◽

Large Delay ◽

Delay Fault ◽

Path Delay Fault ◽

Delay Defects

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Improving diagnostic resolution of delay faults using path delay fault model

Proceedings. 21st VLSI Test Symposium, 2003. ◽

10.1109/vtest.2003.1197673 ◽

2003 ◽

Cited By ~ 5

Author(s):

A.K. Majhi ◽

G. Gronthoud ◽

C. Hora ◽

M. Lousberg ◽

P. Valer ◽

...

Keyword(s):

Fault Model ◽

Delay Faults ◽

Path Delay ◽

Delay Fault ◽

Path Delay Fault ◽

Diagnostic Resolution

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Integration of Learning Techniques into Incremental Satisfiability for Efficient Path-Delay Fault Test Generation

10.1109/date.2005.187 ◽

2005 ◽

Cited By ~ 11

Author(s):

K. Chandrasekar ◽

M.S. Hsiao

Keyword(s):

Test Generation ◽

Path Delay ◽

Delay Fault ◽

Learning Techniques ◽

Path Delay Fault ◽

Integration Of Learning

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A new classification of path-delay fault testability in terms of stuck-at faults

Journal of Computer Science and Technology ◽

10.1007/bf02973460 ◽

2004 ◽

Vol 19 (6) ◽

pp. 955-964 ◽

Cited By ~ 2

Author(s):

Subhashis Majumder ◽

Bhargab B. Bhattacharya ◽

Vishwani D. Agrawal ◽

Michael L. Bushnell

Keyword(s):

Path Delay ◽

New Classification ◽

Delay Fault ◽

Path Delay Fault

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Path Delay Fault Classification

Frontiers in Electronic Testing - Delay Fault Testing for VLSI Circuits ◽

10.1007/978-1-4615-5597-1_5 ◽

1998 ◽

pp. 45-76

Author(s):

Angela Krstić ◽

Kwang-Ting Cheng

Keyword(s):

Fault Classification ◽

Path Delay ◽

Delay Fault ◽

Path Delay Fault

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NEST: a nonenumerative test generation method for path delay faults in combinational circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.476581 ◽

1995 ◽

Vol 14 (12) ◽

pp. 1505-1515 ◽

Cited By ~ 30

Author(s):

I. Pomeranz ◽

S.M. Reddy ◽

P. Uppaluri

Keyword(s):

Test Generation ◽

Delay Faults ◽

Path Delay ◽

Combinational Circuits ◽

Path Delay Faults

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