An approach to test compaction for scan circuits that enhances at-speed testing

Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) ◽

10.1109/dac.2001.935495 ◽

2002 ◽

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Test Compaction ◽

Scan Circuits

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A new approach to test generation and test compaction for scan circuits

2003 Design, Automation and Test in Europe Conference and Exhibition ◽

10.1109/date.2003.1253735 ◽

2003 ◽

Cited By ~ 12

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Test Generation ◽

New Approach ◽

Test Compaction ◽

Scan Circuits

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Static Test Compaction for Scan Circuits by Using Restoration to Modify and Remove Tests

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2014.2358932 ◽

2014 ◽

Vol 33 (12) ◽

pp. 1955-1964 ◽

Cited By ~ 5

Author(s):

Irith Pomeranz

Keyword(s):

Static Test ◽

Test Compaction ◽

Scan Circuits

Download Full-text

An approach to test compaction for scan circuits that enhances at-speed testing

Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) ◽

10.1145/378239.378390 ◽

2001 ◽

Cited By ~ 3

Author(s):

Irith Pomeranz ◽

Sudhakar Reddy

Keyword(s):

Test Compaction ◽

Scan Circuits

Download Full-text

Static test compaction for full-scan circuits based on combinational test sets and non-scan sequential test sequences

16th International Conference on VLSI Design, 2003. Proceedings. ◽

10.1109/icvd.2003.1183159 ◽

2003 ◽

Cited By ~ 4

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Sequential Test ◽

Static Test ◽

Test Compaction ◽

Full Scan ◽

Test Sets ◽

Scan Circuits

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Static test compaction for diagnostic test sets of full-scan circuits

IET Computers & Digital Techniques ◽

10.1049/iet-cdt.2009.0110 ◽

2010 ◽

Vol 4 (5) ◽

pp. 365-373 ◽

Cited By ~ 1

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Diagnostic Test ◽

Static Test ◽

Test Compaction ◽

Full Scan ◽

Test Sets ◽

Scan Circuits

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Static test compaction for full-scan circuits based on combinational test sets and nonscan input sequences and a lower bound on the number of tests

IEEE Transactions on Computers ◽

10.1109/tc.2004.118 ◽

2004 ◽

Vol 53 (12) ◽

pp. 1569-1581 ◽

Cited By ~ 1

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Lower Bound ◽

Static Test ◽

Test Compaction ◽

Full Scan ◽

Test Sets ◽

Scan Circuits

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Transparent scan: a new approach to test generation and test compaction for scan circuits that incorporates limited scan operations

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2003.819424 ◽

2003 ◽

Vol 22 (12) ◽

pp. 1663-1670 ◽

Cited By ~ 13

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Test Generation ◽

New Approach ◽

Test Compaction ◽

Scan Circuits

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POSTT: Path-oriented static test compaction for transition faults in scan circuits

2017 IEEE International Test Conference (ITC) ◽

10.1109/test.2017.8242073 ◽

2017 ◽

Author(s):

Irith Pomeranz

Keyword(s):

Static Test ◽

Test Compaction ◽

Transition Faults ◽

Scan Circuits

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Static test compaction for multiple full-scan circuits

Proceedings 21st International Conference on Computer Design ◽

10.1109/iccd.2003.1240926 ◽

2004 ◽

Cited By ~ 1

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Static Test ◽

Test Compaction ◽

Full Scan ◽

Scan Circuits

Download Full-text

Test compaction for at-speed testing of scan circuits based on nonscan test. sequences and removal of transfer sequences

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2002.1004314 ◽

2002 ◽

Vol 21 (6) ◽

pp. 706-714 ◽

Cited By ~ 6

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Test Compaction ◽

Scan Circuits

Download Full-text