Static test compaction for multiple full-scan circuits

Proceedings 21st International Conference on Computer Design ◽

10.1109/iccd.2003.1240926 ◽

2004 ◽

Cited By ~ 1

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Static Test ◽

Test Compaction ◽

Full Scan ◽

Scan Circuits

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Static test compaction for full-scan circuits based on combinational test sets and non-scan sequential test sequences

16th International Conference on VLSI Design, 2003. Proceedings. ◽

10.1109/icvd.2003.1183159 ◽

2003 ◽

Cited By ~ 4

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Sequential Test ◽

Static Test ◽

Test Compaction ◽

Full Scan ◽

Test Sets ◽

Scan Circuits

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Static test compaction for diagnostic test sets of full-scan circuits

IET Computers & Digital Techniques ◽

10.1049/iet-cdt.2009.0110 ◽

2010 ◽

Vol 4 (5) ◽

pp. 365-373 ◽

Cited By ~ 1

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Diagnostic Test ◽

Static Test ◽

Test Compaction ◽

Full Scan ◽

Test Sets ◽

Scan Circuits

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Static test compaction for full-scan circuits based on combinational test sets and nonscan input sequences and a lower bound on the number of tests

IEEE Transactions on Computers ◽

10.1109/tc.2004.118 ◽

2004 ◽

Vol 53 (12) ◽

pp. 1569-1581 ◽

Cited By ~ 1

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Lower Bound ◽

Static Test ◽

Test Compaction ◽

Full Scan ◽

Test Sets ◽

Scan Circuits

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Static Test Compaction for Scan Circuits by Using Restoration to Modify and Remove Tests

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2014.2358932 ◽

2014 ◽

Vol 33 (12) ◽

pp. 1955-1964 ◽

Cited By ~ 5

Author(s):

Irith Pomeranz

Keyword(s):

Static Test ◽

Test Compaction ◽

Scan Circuits

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POSTT: Path-oriented static test compaction for transition faults in scan circuits

2017 IEEE International Test Conference (ITC) ◽

10.1109/test.2017.8242073 ◽

2017 ◽

Author(s):

Irith Pomeranz

Keyword(s):

Static Test ◽

Test Compaction ◽

Transition Faults ◽

Scan Circuits

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Static Test Compaction using Independent Suffixes of a Transparent-Scan Sequence

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2021.3073625 ◽

2021 ◽

pp. 1-1

Author(s):

Irith Pomeranz

Keyword(s):

Static Test ◽

Test Compaction

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A new approach to test generation and test compaction for scan circuits

2003 Design, Automation and Test in Europe Conference and Exhibition ◽

10.1109/date.2003.1253735 ◽

2003 ◽

Cited By ~ 12

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Test Generation ◽

New Approach ◽

Test Compaction ◽

Scan Circuits

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A static test compaction technique for combinational circuits based on independent fault clustering

10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 ◽

10.1109/icecs.2003.1301757 ◽

2004 ◽

Cited By ~ 2

Author(s):

Y.E. Osais ◽

A.H. El-Maleh

Keyword(s):

Combinational Circuits ◽

Static Test ◽

Test Compaction

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Test Strength: A Quality Metric for Transition Fault Tests in Full-Scan Circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2010.2057459 ◽

2011 ◽

Vol 19 (10) ◽

pp. 1907-1911

Author(s):

Irith Pomeranz ◽

Sudhakar M. Reddy

Keyword(s):

Quality Metric ◽

Transition Fault ◽

Full Scan ◽

Scan Circuits

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Static test compaction for scan-based designs to reduce test application time

Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259) ◽

10.1109/ats.1998.741614 ◽

2002 ◽

Cited By ~ 37

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Application Time ◽

Static Test ◽

Test Compaction ◽

Test Application Time ◽

Test Application

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