Architecture for Reliable Scan-Dump in the Presence of Multiple Asynchronous Clock Domains in FPGA SoCs

2017 ◽  
Author(s):  
Amitava Majumdar ◽  
Balakrishna Jayadev ◽  
Da Cheng ◽  
Albert Lin
Keyword(s):  
Clock Domains

Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains

2010 ◽  
Vol 29 (2) ◽  
pp. 299-312 ◽  
Author(s):  
Laung-Terng Wang ◽  
Xiaoqing Wen ◽  
Shianling Wu ◽  
Hiroshi Furukawa ◽  
Hao-Jan Chao ◽  
...  
Keyword(s):  
Clock Domains

A synchronous interface for SoCs with multiple clock domains

2004 ◽  
Author(s):  
V. Sathe ◽  
C. Ziesler ◽  
M. Papaefthymiou ◽  
Suhwan Kim ◽  
S. Kosonocky
Keyword(s):  
Clock Domains

Clock Domains Cross FIFO Interface Design of Multichannel Continuous DDR2 Read and Write

2014 ◽  
Vol 556-562 ◽  
pp. 1622-1626
Author(s):  
Guo Cheng Wang ◽  
Yan Peng Ma ◽  
Hai Tao Lu ◽  
Xuan Qi Chen ◽  
Ping Li
Keyword(s):  
User Interface ◽  
Interface Design ◽  
Data Stream ◽  
State Machine ◽  
Data Conversion ◽  
Final Design ◽  
Refresh Cycle ◽  
Handshake Protocol ◽  
Clock Domains ◽  
Core Issues

In this paper, a clock domains cross FIFO interface of multichannel continuous DDR2 read and write is designed. The interface provides continuous data stream from DDR2 to 12 different channels simultaneously. Four core issues are resolved: mismatch on bit width between DDR2 user interface and the channels, data stream conversion control from DDR2 to channels, clock domains difference between DDR2 and channels, Discontinuous process of DDR2 read and write. DDR2 storage spaces are partitioned for matching data width of the DDR2 user interface and the channels, and to achieve the maximum utilization of the DDR2 memory. Via state machine, data conversion and synchronization from DDR2 to channels are implemented, and the state machine can be applied to providing continuous DDR2 data to any numbers of channels simultaneously. Cross clock domains FIFO interface goes to solve the different clock domains problem between channels and DDR2. When bank or row addresses conversion occurs, or DDR2 auto-refresh cycle comes, DDR2 cannot be read or written, leading to data interruptedly in time aspect. To solve the problem, the FIFO interface is designed followed the full-mode handshake protocol. Through the interface caching, the 12 channels can continuously read data from the DDR2 simultaneously. The final design can achieve the goal that under the fastest case, DDR2 provides 12 channels data stream simultaneously at 61.538 MHz rate at the same time, and 90.566% efficiency in the reading and writing aspects.

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