A super-grayscale and real-time computer-generated Moiré profilometry using video grating projection

By using the time-division multiplexing characteristics of the projector and the integral exposure characteristics of the charge coupled device (CCD) camera, a super-grayscale and real-time computer-generated Moiré profilometry based on video grating projection is proposed. The traditional digital static grating is of 256-grayscale at most. If an expected super-grayscale grating with a maximum grayscale of 766 is designed and divided into three 256-grayscale fringe patterns with balanced grayscale as far as possible, they can be synthesized into a repeated playing video grating instead of the traditional static grating. When the video grating is projected onto the measured object, as long as the exposure time is set to three times the refresh cycle of the video grating, the super-grayscale deformed patterns in the 766-grayscale can be captured with a 10-bit CCD camera, so that the deformed patterns are realistic. The digital error in computer-generated Moiré profilometry is effectively reduced. In addition, this method can expand the linear range of the deformed pattern by 20% in computer Moiré profilometry. Therefore, the proposed method has the perspectives of high accuracy and real-time measurement. Theoretical analysis and experimental results demonstrate the validity and capability of the proposed method.

Retention-Aware DRAM Auto-Refresh Scheme for Energy and Performance Efficiency

Dynamic random access memory (DRAM) circuits require periodic refresh operations to prevent data loss. As DRAM density increases, DRAM refresh overhead is even worse due to the increase of the refresh cycle time. However, because of few the cells in memory that have lower retention time, DRAM has to raise the refresh frequency to keep the data integrity, and hence produce unnecessary refreshes for the other normal cells, which results in a large refresh energy and performance delay of memory access. In this paper, we propose an integration scheme for DRAM refresh based on the retention-aware auto-refresh (RAAR) method and 2x granularity auto-refresh simultaneously. We also explain the corresponding modification need on memory controllers to support the proposed integration refresh scheme. With the given profile of weak cells distribution in memory banks, our integration scheme can choose the most appropriate refresh technique in each refresh time. Experimental results on different refresh cycle times show that the retention-aware refresh scheme can properly improve the system performance and have a great reduction in refresh energy. Especially when the number of weak cells increased due to the thermal effect of 3D-stacked architecture, our methodology still keeps the same performance and energy efficiency.

Clock Domains Cross FIFO Interface Design of Multichannel Continuous DDR2 Read and Write

In this paper, a clock domains cross FIFO interface of multichannel continuous DDR2 read and write is designed. The interface provides continuous data stream from DDR2 to 12 different channels simultaneously. Four core issues are resolved: mismatch on bit width between DDR2 user interface and the channels, data stream conversion control from DDR2 to channels, clock domains difference between DDR2 and channels, Discontinuous process of DDR2 read and write. DDR2 storage spaces are partitioned for matching data width of the DDR2 user interface and the channels, and to achieve the maximum utilization of the DDR2 memory. Via state machine, data conversion and synchronization from DDR2 to channels are implemented, and the state machine can be applied to providing continuous DDR2 data to any numbers of channels simultaneously. Cross clock domains FIFO interface goes to solve the different clock domains problem between channels and DDR2. When bank or row addresses conversion occurs, or DDR2 auto-refresh cycle comes, DDR2 cannot be read or written, leading to data interruptedly in time aspect. To solve the problem, the FIFO interface is designed followed the full-mode handshake protocol. Through the interface caching, the 12 channels can continuously read data from the DDR2 simultaneously. The final design can achieve the goal that under the fastest case, DDR2 provides 12 channels data stream simultaneously at 61.538 MHz rate at the same time, and 90.566% efficiency in the reading and writing aspects.

The Effects of Repeated Refresh Cycles on the Oxide Integrity of EEPROM Memories at High Temperature

Data retention in stored-charge based memories, such as Flash and EEPROMs, decreases with increasing temperature. Compensation for this shortening of retention time can be accomplished by refreshing the data using periodic erase-write refresh cycles, although the number of these cycles is limited by oxide integrity. An alternate approach is to use refresh cycles consisting of a rewrite only cycles, without the prior erase cycle. The viability of this approach requires that this refresh cycle induces less damage than an erase-write cycle. This paper studies the effects of repeated refresh cycles on oxide integrity in a high temperature environment and makes comparisons to the damage caused by erase-write cycles. The experiment consisted of running a large number of refresh cycles on a selected byte. The control group was other bytes which were not subjected to refresh only cycles. The oxide integrity was checked by performing repeated erase-write cycles on each of the two groups to determine if the refresh cycles decreased the number of erase-write cycles before failure. Data was collected from multiple parts, with different numbers of refresh cycles, and at temperatures ranging from 25C to 190C. The experiment was conducted on microcontrollers containing embedded EEPROM memories. The microcontrollers were programmed to test and measure their own memories, and to report the results to an external controller. This greatly simplified the hardware setup, since only six wires were required to operate and test the memories of 77 microcontrollers. It also allowed data collection from the microcontrollers while the experiment was in progress. Data is presented showing that refresh cycles do not have a significant impact on oxide integrity. This result shows that the refresh cycle approach will not degrade the oxide and suggests that it will provide a mechanism to extend data retention at high temperatures without affecting device reliability. The data also showed a bimodal distribution of the number of erase-write cycles necessary to damage the oxide. Although the cause of this distribution is not yet understood, it may provide an additional means to significantly improve EEPROM reliability through appropriate screening.

Study on Influence of Different Desulfurization Methods of Apple Slice

In order to decrease the residue content of sulfite of apple slices, the desulfurization by water, alkali solution and ultrasonic were studied. Results showed that the optimal parameters of the orthogonal design for eliminating the sulfur by water were: 60°C of temperature, 1:6 of solid-liquid ratio, 45 min/time of water refresh cycle, 3h of time. In this optimal condition, the desulfurization was 96.054%, and the residue content of sulfite was 0.090 g/kg. While the optimum conditions of alkali method were: using 0.06% Ca (OH) 2 with the solid-liquid ratio 1:5.4 at 54°C. In this optimal condition, the desulfurization rate was 96.673%, and the residue content was down to 0.076g/kg.The optimal parameters for eliminating the sulfur by ultrasonic were: solid-liquid ratio1:6, treatment time 25 min, ultrasonic power 120w, temperature 35°C. In this optimal condition, the desulfurization rate was 97.418%, and the residue content of sulfite was only 0.059g/kg.