clock domains Latest Research Papers

Advancement in Onchip Clocking to Improve ATPG Coverage Between Clock Domains

Advances in Automation, Signal Processing, Instrumentation, and Control - Lecture Notes in Electrical Engineering ◽

10.1007/978-981-15-8221-9_95 ◽

2021 ◽

pp. 1011-1019

Author(s):

Ramesh Devani ◽

Mayankkumar Kapadiya ◽

Piyush M. Chaniyara

Keyword(s):

Clock Domains

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SpaceWire Receiver: Synchronization for Different Clock Domains

Proceedings of the 4th Brazilian Technology Symposium (BTSym'18) - Smart Innovation, Systems and Technologies ◽

10.1007/978-3-030-16053-1_4 ◽

2019 ◽

pp. 35-44

Author(s):

Alexsander Deucher ◽

Angela Alves dos Santos ◽

Antonio Carlos da Costa Telles ◽

Saulo Finco

Keyword(s):

Clock Domains

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High-Level Synthesis of FPGA Circuits with Multiple Clock Domains

2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) ◽

10.1109/fccm.2018.00026 ◽

2018 ◽

Cited By ~ 1

Author(s):

Omar Ragheb ◽

Jason H. Anderson

Keyword(s):

High Level Synthesis ◽

Clock Domains ◽

High Level

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Architecture for Reliable Scan-Dump in the Presence of Multiple Asynchronous Clock Domains in FPGA SoCs

2017 IEEE 26th Asian Test Symposium (ATS) ◽

10.1109/ats.2017.36 ◽

2017 ◽

Cited By ~ 1

Author(s):

Amitava Majumdar ◽

Balakrishna Jayadev ◽

Da Cheng ◽

Albert Lin

Keyword(s):

Clock Domains

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A novel sequence latched synchronizer design interface for asynchronous clock domains

2017 International Conference on Signal Processing and Communication (ICSPC) ◽

10.1109/cspc.2017.8305882 ◽

2017 ◽

Author(s):

S Sreeja ◽

R Mithun

Keyword(s):

Clock Domains

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Design of a Self-Timed Data Synchronizer for Crossing Two Different Clock Domains

International Journal of Computer Applications ◽

10.5120/ijca2017913008 ◽

2017 ◽

Vol 159 (8) ◽

pp. 17-22

Author(s):

Hatem M. ◽

Rehab I.

Keyword(s):

Clock Domains

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A Study of 3-D Power Delivery Networks With Multiple Clock Domains

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2016.2549275 ◽

2016 ◽

Vol 24 (11) ◽

pp. 3218-3231 ◽

Cited By ~ 6

Author(s):

Aida Todri-Sanial ◽

Yuanqing Cheng

Keyword(s):

Power Delivery ◽

Power Delivery Networks ◽

Clock Domains ◽

Delivery Networks

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Low Latency Synchronization Scheme Using Prediction and Avoidance of Synchronization Failure in Heterochronous Clock Domains

JSTS Journal of Semiconductor Technology and Science ◽

10.5573/jsts.2015.15.2.208 ◽

2015 ◽

Vol 15 (2) ◽

pp. 208-222 ◽

Cited By ~ 1

Author(s):

Sung-Gun Song ◽

Seong-Mo Park ◽

Jeong-Gun Lee ◽

Myeong-Hoon Oh

Keyword(s):

Low Latency ◽

Clock Domains ◽

Synchronization Scheme

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Online Binding of Applications to Multiple Clock Domains in Shared FPGA-based Systems

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015 ◽

10.7873/date.2015.0409 ◽

2015 ◽

Cited By ~ 2

Author(s):

Farzad Samie ◽

Lars Bauer ◽

Chih-Ming Hsieh ◽

Jörg Henkel

Keyword(s):

Clock Domains

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An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e98.a.1376 ◽

2015 ◽

Vol E98.A (7) ◽

pp. 1376-1391

Author(s):

Shin-ya ABE ◽

Youhua SHI ◽

Kimiyoshi USAMI ◽

Masao YANAGISAWA ◽

Nozomu TOGAWA

Keyword(s):

Energy Efficient ◽

High Level Synthesis ◽

Synthesis Algorithm ◽

Clock Domains ◽

High Level

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clock domains
Recently Published Documents

TOTAL DOCUMENTS

H-INDEX

Advancement in Onchip Clocking to Improve ATPG Coverage Between Clock Domains

SpaceWire Receiver: Synchronization for Different Clock Domains

High-Level Synthesis of FPGA Circuits with Multiple Clock Domains

Architecture for Reliable Scan-Dump in the Presence of Multiple Asynchronous Clock Domains in FPGA SoCs

A novel sequence latched synchronizer design interface for asynchronous clock domains

Design of a Self-Timed Data Synchronizer for Crossing Two Different Clock Domains

A Study of 3-D Power Delivery Networks With Multiple Clock Domains

Low Latency Synchronization Scheme Using Prediction and Avoidance of Synchronization Failure in Heterochronous Clock Domains

Online Binding of Applications to Multiple Clock Domains in Shared FPGA-based Systems

An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design

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clock domainsRecently Published Documents

TOTAL DOCUMENTS

H-INDEX

Advancement in Onchip Clocking to Improve ATPG Coverage Between Clock Domains

SpaceWire Receiver: Synchronization for Different Clock Domains

High-Level Synthesis of FPGA Circuits with Multiple Clock Domains

Architecture for Reliable Scan-Dump in the Presence of Multiple Asynchronous Clock Domains in FPGA SoCs

A novel sequence latched synchronizer design interface for asynchronous clock domains

Design of a Self-Timed Data Synchronizer for Crossing Two Different Clock Domains

A Study of 3-D Power Delivery Networks With Multiple Clock Domains

Low Latency Synchronization Scheme Using Prediction and Avoidance of Synchronization Failure in Heterochronous Clock Domains

Online Binding of Applications to Multiple Clock Domains in Shared FPGA-based Systems

An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design

clock domains
Recently Published Documents