A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips

2005 ◽  
Author(s):  
A.K. Palit ◽  
Lei Wu ◽  
K.K. Duganapalli ◽  
W. Anheier ◽  
J. Schloeffel
Keyword(s):  
Signal Integrity ◽  
Fault Model ◽  
Deep Submicron ◽  
Coupling Noise

Resistive Bridge fault model evolution from conventional to ultra deep submicron

2005 ◽  
Author(s):  
I. Polian ◽  
P. Engelke ◽  
B. Becker ◽  
S. Kundu ◽  
J.-M. Galliere ◽  
...  
Keyword(s):  
Fault Model ◽  
Deep Submicron ◽  
Model Evolution

scholarly journals A Novel Per-Test Fault Diagnosis Method Based on the Extended X-Fault Model for Deep-Submicron LSI Circuits

2008 ◽  
Vol E91-D (3) ◽  
pp. 667-674 ◽  
Author(s):  
Y. YAMATO ◽  
Y. NAKAMURA ◽  
K. MIYASE ◽  
X. WEN ◽  
S. KAJIHARA
Keyword(s):  
Fault Diagnosis ◽  
Fault Model ◽  
Deep Submicron ◽  
Diagnosis Method

Signal integrity problems in deep submicron arising from interconnects between cores

2002 ◽  
Author(s):  
P. Nordholz ◽  
D. Treytnar ◽  
J. Otterstedt ◽  
H. Grabinski ◽  
D. Niggemeyer ◽  
...  
Keyword(s):  
Signal Integrity ◽  
Deep Submicron

EARLY BUFFER PLANNING WITH CONGESTION CONTROL USING BUFFER REQUIREMENT MAP

2010 ◽  
Vol 19 (05) ◽  
pp. 949-973
Author(s):  
ALI JAHANIAN ◽  
MORTEZA SAHEB ZAMANI
Keyword(s):  
Signal Integrity ◽  
Deep Submicron ◽  
Design Flow ◽  
Buffer Insertion ◽  
Design Quality ◽  
Circuit Performance ◽  
Buffer Planning ◽  
Planning Algorithm ◽  
Buffer Requirement ◽  
Time Overhead

Buffer insertion plays an important role in circuit performance and signal integrity especially in deep submicron technologies. The stage at which buffers are inserted in a design has a large impact on the design quality. Early buffer insertion may cause misestimation due to unknown cell locations whereas buffer insertion after placement may not be very effective because the cell locations have been fixed and buffer resources may be distributed inappropriately. In this paper, a buffer planning algorithm for floor-placement design flow is presented. This algorithm creates a map of buffer requirements in various regions of the design at the floorplanning stage and then enforces the detailed placer to distribute white spaces with respect to the estimated buffer requirement map. Experimental results show that the proposed method improves the performance of attempted circuits with fewer buffers. Furthermore, results show that congestion, routability and design convergence are improved and the auxiliary loops are avoided in the proposed design flow. Our analyses and experiments show that the CPU time overhead of this algorithm is very small.

Nosie and signal integrity in deep submicron design (panel)

1997 ◽  
Author(s):  
William E. Guthrie ◽  
Massaud Pedram ◽  
Wayne Dai ◽  
Rakesh Chadha ◽  
Jason Cong ◽  
...  
Keyword(s):  
Signal Integrity ◽  
Deep Submicron
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