Signal integrity problems in deep submicron arising from interconnects between cores

Buffer insertion plays an important role in circuit performance and signal integrity especially in deep submicron technologies. The stage at which buffers are inserted in a design has a large impact on the design quality. Early buffer insertion may cause misestimation due to unknown cell locations whereas buffer insertion after placement may not be very effective because the cell locations have been fixed and buffer resources may be distributed inappropriately. In this paper, a buffer planning algorithm for floor-placement design flow is presented. This algorithm creates a map of buffer requirements in various regions of the design at the floorplanning stage and then enforces the detailed placer to distribute white spaces with respect to the estimated buffer requirement map. Experimental results show that the proposed method improves the performance of attempted circuits with fewer buffers. Furthermore, results show that congestion, routability and design convergence are improved and the auxiliary loops are avoided in the proposed design flow. Our analyses and experiments show that the CPU time overhead of this algorithm is very small.

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Nosie and signal integrity in deep submicron design (panel)

Proceedings of the 34th annual conference on Design automation conference - DAC '97 ◽

10.1145/266021.266352 ◽

1997 ◽

Cited By ~ 1

Author(s):

William E. Guthrie ◽

Massaud Pedram ◽

Wayne Dai ◽

Rakesh Chadha ◽

Jason Cong ◽

...

Keyword(s):

Signal Integrity ◽

Deep Submicron

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Tuning Strategies for Global Interconnects in High-Performance Deep-Submicron ICs

VLSI Design ◽

10.1155/1999/38974 ◽

1999 ◽

Vol 10 (1) ◽

pp. 21-34 ◽

Cited By ~ 14

Author(s):

Andrew B. Kahng ◽

Sudhakar Muddu ◽

Egino Sarto

Keyword(s):

High Performance ◽

Signal Integrity ◽

Leading Edge ◽

Deep Submicron ◽

Worst Case ◽

Optimal Interval ◽

Bus Routing ◽

Optimum Technique ◽

Global Interconnects ◽

And Performance

Interconnect tuning is an increasingly critical degree of freedom in the physical design of high-performance VLSI systems. By interconnect tuning, we refer to the selection of line thicknesses, widths and spacings in multi-layer interconnect to simultaneously optimize signal distribution, signal performance, signal integrity, and interconnect manufacturability and reliability. This is a key activity in most leading-edge design projects, but has received little attention in the literature. Our work provides the first technology-specific studies of interconnect tuning in the literature. We center on global wiring layers and interconnect tuning issues related to bus routing, repeater insertion, and choice of shielding/spacing rules for signal integrity and performance. We address four basic questions. (1) How should width and spacing be allocated to maximize performance for a given line pitch? (2) For a given line pitch, what criteria affect the optimal interval at which repeaters Should be inserted into global interconnects? (3) Under what circumstances are shield wires the optimum technique for improving interconnect performance? (4) In global interconnect with repeaters, what other interconnect tuning is possible? Our study of question (4) demonstrates a new approach of offsetting repeater placements that can reduce worst-case cross-chip delays by over 30% in current technologies.

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